Amin Rezaei

Orcid: 0000-0002-7469-3642

Affiliations:
  • California State University, Long Beach, CA, USA
  • Northwestern University, Evanston, IL, USA
  • University of Louisiana at Lafayette, LA, USA
  • Shahid Beheshti University (SBU), Department of Computer Engineering, Tehran, Iran


According to our database1, Amin Rezaei authored at least 44 papers between 2014 and 2024.

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Bibliography

2024
Machine Learning-Based Security Evaluation and Overhead Analysis of Logic Locking.
J. Hardw. Syst. Secur., March, 2024

Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

CycPUF: Cyclic Physical Unclonable Function.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Reliable and secure memristor-based chaotic communication against eavesdroppers and untrusted foundries.
Discov. Internet Things, December, 2023

Machine Learning in Chaos-Based Encryption: Theory, Implementations, and Applications.
IEEE Access, 2023

Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

DK Lock: Dual Key Logic Locking Against Oracle-Guided Attacks.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Risk-Aware and Explainable Framework for Ensuring Guaranteed Coverage in Evolving Hardware Trojan Detection.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

CoLA: Convolutional Neural Network Model for Secure Low Overhead Logic Locking Assignment.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Evaluating the Security of eFPGA-Based Redaction Algorithms.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Global Attack and Remedy on IC-Specific Logic Encryption.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Distributed Logic Encryption: Essential Security Requirements and Low-Overhead Implementation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Sequential Logic Encryption Against Model Checking Attack.
IACR Cryptol. ePrint Arch., 2021

Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries.
IACR Cryptol. ePrint Arch., 2021

A Comprehensive Analysis of Chaos-Based Secure Systems.
Proceedings of the Silicon Valley Cybersecurity Conference - Second Conference, 2021

Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Malware Detection using Microarchitectural Events.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Discrete Time Delay Feedback Control of Stewart Platform with Intelligent Optimizer Weight Tuner.
Proceedings of the IEEE International Conference on Robotics and Automation, 2021

2020
KNN-enhanced Deep Learning Against Noisy Labels.
CoRR, 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

2019
A fault-tolerant and congestion-aware architecture for wireless networks-on-chip.
Wirel. Networks, 2019

An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip.
J. Supercomput., 2019

Vulnerability and Remedy of Stripped Function Logic Locking.
IACR Cryptol. ePrint Arch., 2019

Resolving the Trilemma in Logic Encryption.
IACR Cryptol. ePrint Arch., 2019

BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption.
IACR Cryptol. ePrint Arch., 2019

SigAttack: New High-level SAT-based Attack on Logic Encryptions.
IACR Cryptol. ePrint Arch., 2019

Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation.
IACR Cryptol. ePrint Arch., 2019

CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States.
IACR Cryptol. ePrint Arch., 2019

Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
Chapter Three - Multiobjectivism in Dark Silicon Age.
Adv. Comput., 2018

HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era.
Microprocess. Microsystems, 2017

SAT-based Bit-flipping Attack on Logic Encryptions.
IACR Cryptol. ePrint Arch., 2017

A Comparative Investigation of Approximate Attacks on Logic Encryptions.
IACR Cryptol. ePrint Arch., 2017

Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks.
IACR Cryptol. ePrint Arch., 2017

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

2016
Hierarchical approach for hybrid wireless Network-on-chip in many-core era.
Comput. Electr. Eng., 2016

SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Efficient Congestion-Aware Scheme for Wireless on-Chip Networks.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Dynamic Application Mapping Algorithm for Wireless Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

2014
HiWA: A hierarchical Wireless Network-on-Chip architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014


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