Amin Jarrah

Orcid: 0000-0001-8039-190X

According to our database1, Amin Jarrah authored at least 22 papers between 2013 and 2023.

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Bibliography

2023
Automotive engine idle speed controller: Nonlinear model predictive control utilizing the firefly algorithm.
Comput. Electr. Eng., May, 2023

2022
Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study.
J. King Saud Univ. Comput. Inf. Sci., 2022

FCM Clustering Approach Optimization Using Parallel High-Speed Intel FPGA Technology.
J. Electr. Comput. Eng., 2022

High Performance Changeable Dynamic Gentle Random Early Detection (CDGRED) for Congestion Control at Router Buffer.
Int. J. Grid High Perform. Comput., 2022

Optimised implementation of AVR system using particle swarm optimisation.
Int. J. Comput. Sci. Eng., 2022

The optimisation of travelling salesman problem based on parallel ant colony algorithm.
Int. J. Comput. Appl. Technol., 2022

High Performance Implementation of Neural Networks Learning Using Swarm Optimization Algorithms for EEG Classification Based on Brain Wave Data.
Int. J. Appl. Metaheuristic Comput., 2022

2021
High-Performance Implementation of Wideband Coherent Signal-Subspace (CSS)-Based DOA Algorithm on FPGA.
J. Circuits Syst. Comput., 2021

2020
An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology.
South Afr. Comput. J., 2020

Parallel implementation of genetic algorithm on FPGA using Vivado high level synthesis.
Int. J. Bio Inspired Comput., 2020

2018
Optimized Parallel Implementation of Extended Kalman Filter Using FPGA.
J. Circuits Syst. Comput., 2018

2017
Optimized parallel architecture of evolutionary neural network for mass spectrometry data processing.
Int. J. Model. Simul. Sci. Comput., 2017

2016
A Parallel Implementation of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR) on a GPU.
J. Signal Process. Syst., 2016

FPGA based architecture of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR).
Microprocess. Microsystems, 2016

2015
Reconfigurable FPGA/GPU-Based Architecture of Block Compressive Sampling Matching Pursuit Algorithm.
J. Circuits Syst. Comput., 2015

Parralelization of non-linear & non-Gaussian Bayesian state estimators (Particle filters).
Proceedings of the 23rd European Signal Processing Conference, 2015

2014
Optimized FPGA based implementation of discrete wavelet transform.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Power Reduction Technique using Multiple Supply voltage and Switching Activity Analysis.
J. Circuits Syst. Comput., 2013

Semi-Automatic Cracks Correction Based on seam Processing, stochastic Analysis and Learning Process.
Int. J. Image Graph., 2013

A parallel implementation of IR video processing on a GPU.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Energy analysis and NoC design for heterogeneous MPSoC platform for a video application.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Software tool for FPGA based MIMO radar applications.
Proceedings of the 2013 Asilomar Conference on Signals, 2013


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