Amin Jadidi

Orcid: 0000-0002-6208-4540

According to our database1, Amin Jadidi authored at least 12 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

2018
Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs.
IEEE Trans. Computers, 2018

Tolerating Write Disturbance Errors in PCM: Experimental Characterization, Analysis, and Mechanisms.
Proceedings of the 26th IEEE International Symposium on Modeling, 2018

Hybrid-comp: A criticality-aware compressed last-level cache.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
HL-PCM: MLC PCM Main Memory with Accelerated Read.
IEEE Trans. Parallel Distributed Syst., 2017

Optimizing energy consumption in GPUS through feedback-driven CTA scheduling.
Proceedings of the 25th High Performance Computing Symposium, Virginia Beach, VA, USA, April 23, 2017

A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems.
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05, 2017

Leveraging value locality for efficient design of a hybrid cache in multicore processors.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017

2016
MLC PCM main memory with accelerated read.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2011
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A morphable phase change memory architecture considering frequent zero values.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011


  Loading...