Amin Farmahini Farahani

According to our database1, Amin Farmahini Farahani authored at least 20 papers between 2006 and 2020.

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Bibliography

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

2019
Power Profiling of Modern Die-Stacked Memory.
IEEE Comput. Archit. Lett., 2019

2018
Challenges of High-Capacity DRAM Stacks and Potential Directions.
Proceedings of the Workshop on Memory Centric High Performance Computing, 2018

RegMutex: Inter-Warp GPU Register Time-Sharing.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2016
Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules.
IEEE Micro, 2016

Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
DRAMA: An Architecture for Accelerated Processing Near Memory.
IEEE Comput. Archit. Lett., 2015

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

NMI: A new memory interface to enable innovation.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014
Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Modular Design of High-Throughput, Low-Latency Sorting Units.
IEEE Trans. Computers, 2013

2011
Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron Collider.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

2010
Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization.
Eng. Appl. Artif. Intell., 2010

2009
FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider.
Proceedings of the FCCM 2009, 2009

2008
Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Simulation of Voice Processing Applications through VLIW DSP Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

SOPC-Based Architecture for Discrete Particle Swarm Optimization.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

HW/SW partitioning using discrete particle swarm.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Parallel-Genetic-Algorithm-Based HW/SW Partitioning.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006


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