Amin Chegeni

According to our database, Amin Chegeni authored at least 4 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2018

A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs.

Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2012

CMOS implementation of a fast 4-2 compressor for parallel accumulations.

Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei, Amin Chegeni

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Input dependent clock jitter in high speed and high resolution ADCs.

Amin Chegeni, Reza Shayanfar, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2007

Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure.

Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the 14th IEEE International Conference on Electronics, 2007