Amin Aghighi

Orcid: 0000-0002-1177-0882

According to our database1, Amin Aghighi authored at least 8 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive.
IEEE J. Solid State Circuits, May, 2024

2020
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

An ULP Self-Supplied Brain Interface Circuit.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector.
Proceedings of the VLSI-SoC: Design Trends, 2020

Energy and Area Efficient Mixed-Mode MCMC MIMO Detector.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019
CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2016
A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016


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