Ameya Bhide

According to our database, Ameya Bhide authored at least 8 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters.

Ameya Bhide

PhD thesis, 2015

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved ΔΣ DACs.

Ameya Bhide, Amin Ojani, Atila Alvandpour

IEEE Trans. Circuits Syst. II Express Briefs, 2015

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS.

Ameya Bhide, Atila Alvandpour

IEEE J. Solid State Circuits, 2015

2014

Timing challenges in high-speed interleaved ΔΣ DACs.

Ameya Bhide, Atila Alvandpour

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS.

Ameya Bhide, Omid Esmailzadeh Najari, Behzad Mesgarzadeh, Atila Alvandpour

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators.

Ameya Bhide, Atila Alvandpour

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2012

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for Medical Implant Devices.

Dai Zhang, Ameya Bhide, Atila Alvandpour

IEEE J. Solid State Circuits, 2012

2011

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices.

Dai Zhang, Ameya Bhide, Atila Alvandpour

Proceedings of the 37th European Solid-State Circuits Conference, 2011