Amer Baghdadi
Orcid: 0000-0002-6181-6500
According to our database1,
Amer Baghdadi
authored at least 102 papers
between 2000 and 2024.
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Bibliography
2024
IEEE Trans. Wirel. Commun., August, 2024
2023
Novel transmission technique based on intentional overlapping for spectral efficiency enhancement in multicarrier systems.
Proceedings of the 34th IEEE Annual International Symposium on Personal, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping.
J. Circuits Syst. Comput., 2022
Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes.
IEEE Access, 2022
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning.
Proceedings of the Advances in System-Integrated Intelligence, 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes.
Proceedings of the 11th International Symposium on Signal, Image, Video and Communications, 2022
Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping.
Des. Autom. Embed. Syst., 2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the International Workshop on Rapid System Prototyping, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
J. Circuits Syst. Comput., 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation.
IEEE Trans. Veh. Technol., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Access, 2018
Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018
NISC Design Experience of Flexible Architectures for Digital Communication Applications.
Proceedings of the 2018 International Conference on Computer and Applications (ICCA), 2018
Proceedings of the 2018 IEEE International Conference on Communications, 2018
2017
Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping.
EURASIP J. Embed. Syst., 2017
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Signal Process., 2017
High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards.
IEEE Access, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 29th International Conference on Microelectronics, 2017
Proceedings of the 29th International Conference on Microelectronics, 2017
2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Circuits Syst. Signal Process., 2015
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015
2014
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding.
IET Commun., 2014
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization.
Proceedings of the Third International Conference on Communications and Information Technology, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
VLSI Design, 2012
IEEE Trans. Signal Process., 2012
EURASIP J. Adv. Signal Process., 2012
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012
Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm<sup>2</sup> multi-standard turbo decoder.
Proceedings of the 2012 International Symposium on System on Chip, 2012
Complexity reduction of shuffled parallel iterative demodulation with turbo decoding.
Proceedings of the 19th International Conference on Telecommunications, 2012
2011
Microprocess. Microsystems, 2011
Proceedings of the 19th International Conference on Software, 2011
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
A low complexity stopping criterion for reducing power consumption in turbo decoders.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
EURASIP J. Adv. Signal Process., 2010
Power consumption analysis and energy efficient optimization for turbo decoder implementation.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Embed. Syst. Lett., 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip.
Int. J. Embed. Syst., 2005
2004
A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip.
Ann. des Télécommunications, 2004
An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
Proceedings of the 41th Design Automation Conference, 2004
2003
Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform.
Des. Autom. Embed. Syst., 2003
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003
2002
Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. (Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC).
PhD thesis, 2002
Tech. Sci. Informatiques, 2002
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.
IEEE Trans. Software Eng., 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
An efficient architecture model for systematic design of application-specific multiprocessor SoC.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000
Generic Architecture Platform for Multiprocessor System-On-Chip Design.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000