Alvin R. Lebeck

Orcid: 0000-0003-1893-5464

Affiliations:
  • Duke University, Durham, USA


According to our database1, Alvin R. Lebeck authored at least 84 papers between 1989 and 2023.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to memory hierarchies and energy-efficient and parallel computing".

Timeline

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Bibliography

2023
RDMA Congestion Control: It Is Only for the Compliant.
IEEE Micro, 2023

Understanding RDMA Microarchitecture Resources for Performance Isolation.
Proceedings of the 20th USENIX Symposium on Networked Systems Design and Implementation, 2023

2022
Fast Convergence to Fairness for Reduced Long Flow Tail Latency in Datacenter Networks.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

2021
Accelerating Markov Random Field Inference with Uncertainty Quantification.
CoRR, 2021

Statistical robustness of Markov chain Monte Carlo accelerators.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Beyond Application End-Point Results: Quantifying Statistical Robustness of MCMC Accelerators.
CoRR, 2020

Lightweight Inter-transaction Caching with Precise Clocks and Dynamic Self-invalidation.
CoRR, 2020

2019
Multi-version Indexing in Flash-based Key-Value Stores.
CoRR, 2019

A Case for Quantifying Statistical Robustness of Specialized Probabilistic AI Accelerators.
CoRR, 2019

Managing Tail Latency in Datacenter-Scale File Systems Under Production Constraints.
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

2018
SandTrap: Tracking Information Flows On Demand with Parallel Permissions.
Proceedings of the 16th Annual International Conference on Mobile Systems, 2018

Adaptive Simultaneous Multi-tenancy for GPUs.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2018

Architecting a Stochastic Computing Unit with Molecular Optical Devices.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic.
IEEE Micro, 2017

Enabling Lightweight Transactions with Precision Time.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Combined Compute and Storage: Configurable Memristor Arrays to Accelerate Search.
CoRR, 2016

Exploiting accelerators for efficient high dimensional similarity search.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing.
IEEE Micro, 2015

mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices.
ACM J. Emerg. Technol. Comput. Syst., 2015

More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Modeling and simulation of a nanoscale optical computing system.
J. Parallel Distributed Comput., 2014

Rhythm: harnessing data parallel hardware for server workloads.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Exploiting emerging technologies for nanoscale photonic networks-on-chip.
Proceedings of the Network on Chip Architectures, 2013

2011
Address Translation Aware Memory Consistency.
IEEE Micro, 2011

2010
Architectural Implications of Nanoscale-Integrated Sensing and Computing.
IEEE Micro, 2010

Routing in self-organizing nano-scale irregular networks.
ACM J. Emerg. Technol. Comput. Syst., 2010

Fractal Consistency: Architecting the Memory System to Facilitate Verification.
IEEE Comput. Archit. Lett., 2010

Fractal Coherence: Scalably Verifiable Cache Coherence.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Specifying and dynamically verifying address translation-aware memory consistency.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Nano-Scale On-Chip Irregular Network Analysis.
Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

Architectural implications of nanoscale integrated sensing and computing.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
Nanoscale Optical Computing Using Resonance Energy Transfer Logic.
IEEE Micro, 2008

Introduction to DAC 2007 special section.
ACM J. Emerg. Technol. Comput. Syst., 2008

2007
A self-organizing defect tolerant SIMD architecture.
ACM J. Emerg. Technol. Comput. Syst., 2007

2006
Spin Detection Hardware for Improved Management of Multithreaded Systems.
IEEE Trans. Parallel Distributed Syst., 2006

NANA: A nano-scale active network architecture.
ACM J. Emerg. Technol. Comput. Syst., 2006

Self-Assembled Networks: Control vs. Complexity.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Panel: Nano-computing - do we need new formal approaches?
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Design automation for DNA self-assembled nanostructures.
Proceedings of the 43rd Design Automation Conference, 2006

A defect tolerant self-organizing nanoscale SIMD architecture.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
Experiences in managing energy with ECOSystem.
IEEE Pervasive Comput., 2005

Self-Assembled Architectures and the Temporal Aspects of Computing.
Computer, 2005

Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution.
Proceedings of the 2005 USENIX Annual Technical Conference, 2005

2004
Exploiting Global Knowledge to Achieve Self-Tuned Congestion Control for k-Ary n-Cube Networks.
IEEE Trans. Parallel Distributed Syst., 2004

Tolerating memory latency through push prefetching for pointer-intensive applications.
ACM Trans. Archit. Code Optim., 2004

Communication breakdown: analyzing CPU usage in commercial Web workloads.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

2003
Currentcy: A Unifying Abstraction for Expressing Energy Management Policies.
Proceedings of the General Track: 2003 USENIX Annual Technical Conference, 2003

Quantifying instruction criticality for shared memory multiprocessors.
Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

BLAM : A High-Performance Routing Algorithm for Virtual Cut-Through Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Recursive Array Layouts and Fast Matrix Multiplication.
IEEE Trans. Parallel Distributed Syst., 2002

Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

A Programmable Memory Hierarchy for Prefetching Linked Data Structures.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

A Large, Fast Instruction Window for Tolerating Cache Misses.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

ECOSystem: managing energy as a first class operating system resource.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2001
The Combinatorics of Cache Misses during Matrix Multiplication.
J. Comput. Syst. Sci., 2001

Exact Analysis of the Cache Behavior of Nested Loops.
Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2001

Memory controller policies for DRAM power management.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Locality vs. criticality.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Self-Tuned Congestion Control for Multiprocessor Networks.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.
IEEE Trans. Computers, 2000

Every joule is precious: the case for revisiting operating system design for energy efficiency.
Proceedings of the 9th ACM SIGOPS European Workshop, 2000

Push vs. pull: data movement for linked data structures.
Proceedings of the 14th international conference on Supercomputing, 2000

Power Aware Page Allocation.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999
Load Latency Tolerance in Dynamically Scheduled Processors.
J. Instr. Level Parallelism, 1999

Recursive Array Layouts and Fast Parallel Matrix Multiplication.
Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999

Cache conscious programming in undergraduate computer science.
Proceedings of the 30th SIGCSE Technical Symposium on Computer Science Education, 1999

Nonlinear array layouts for hierarchical memory systems.
Proceedings of the 13th international conference on Supercomputing, 1999

Annotated Memory References: A Mechanism for Informed Cache Management.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Tuning Strassen's Matrix Multiplication for Memory Efficiency.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

1997
Active Memory: A New Abstraction for Memory System Simulation.
ACM Trans. Model. Comput. Simul., 1997

Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging.
Proceedings of the 6th International Symposium on High Performance Distributed Computing, 1997

1995
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1994
Request Combining in Multiprocessors with Arbitrary Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 1994

Cache Profiling and the SPEC Benchmarks: A Case Study.
Computer, 1994

Application-specific protocols for user-level shared memory.
Proceedings of the Proceedings Supercomputing '94, 1994

Fine-grain Access Control for Distributed Shared Memory.
Proceedings of the ASPLOS-VI Proceedings, 1994

1993
Wisconsin Architectural Research Tool Set.
SIGARCH Comput. Archit. News, 1993

The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers.
Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1993

Mechanisms for Cooperative Shared Memory.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1989
Inexpensive Implementations of Set-Associativity.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989


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