Alvin M. Despain

Affiliations:
  • University of Southern California, Los Angeles, USA


According to our database1, Alvin M. Despain authored at least 68 papers between 1974 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contribution to computer systems implementation".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2006
Design and evaluation of a hierarchical decoupled architecture.
J. Supercomput., 2006

2003
Position error signal estimation at high sampling rates using data and servo sector measurements.
IEEE Trans. Control. Syst. Technol., 2003

HiDISC: A Decoupled Architecture for Data-Intensive Application.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Position error signal estimation at high sampling rates using data and servo sector measurements.
Proceedings of the 41st IEEE Conference on Decision and Control, 2002

1998
Low-power state assignment targeting two- and multilevel logic implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Simulating the Effect of Decoherence and Inaccuracies on a Quantum Computer.
Proceedings of the Quantum Computing and Quantum Communications, 1998

1997
Design and Simulation of the Aquarius-II Multiprocessor.
J. Syst. Integr., 1997

State assignment based on two-dimensional placement and hypercube mapping.
Integr., 1997

1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996

Design and Analysis of Hardware for High-Performance Prolog.
J. Log. Program., 1996

1995
Power estimation methods for sequential logic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Synthesis of application specific instruction sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Cache design trade-offs for power and performance optimization: a case study.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

190-MHz CMOS 4-Kbyte Pipelined Caches.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

PLATO P: PLA Timing Optimization by Partitioning.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Cache designs for energy efficiency.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

A Fast State Assignment Procedure for Large FSMs.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Power efficient technology decomposition and mapping under an extended power consumption model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Saving Power in the Control Path of Embedded Processors.
IEEE Des. Test Comput., 1994

Minimizing branch misprediction penalties for superpipelined processors.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Branch with Masked Squashing in Superpipelined Processors.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

Low power state assignment targeting two-and multi-level logic implementations.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Generating instruction sets and microarchitectures from applications.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
Proceedings of the 31st Conference on Design Automation, 1994

Synthesis of Instruction Sets for Pipelined Microprocessors.
Proceedings of the 31st Conference on Design Automation, 1994

Hardware-software co-designing benchmark-driven superpipelined instruction set processors.
Proceedings of the Eighteenth Annual International Computer Software and Applications Conference, 1994

Lower Power Architecture Design and Compilation Techniques for High-Performance Processors.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994

1993
Prophetic branches: a branch architecture for code compaction and efficient execution.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

The 16-fold way: a microparallel taxonomy.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Efficient estimation of dynamic power consumption under a real delay model.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

PDAS: Processor design automation system.
Proceedings of the European Design Automation Conference 1993, 1993

Technology Decomposition and Mapping Targeting Low Power Dissipation.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
High-Performance Logic Programming with the Aquarius Prolog Compiler.
Computer, 1992

Application-Driven Design Automation for Microprocessor Design.
Proceedings of the 29th Design Automation Conference, 1992

High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers.
Proceedings of the 29th Design Automation Conference, 1992

1991
An integrated prolog architecture for symbolic and numeric executions.
Ann. Math. Artif. Intell., 1991

Viewing Instruction Set Design as an Optimization Problem.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

AI and Design.
Proceedings of the 12th International Joint Conference on Artificial Intelligence. Sydney, 1991

1990
The Performance of Parallel Prolog Programs.
IEEE Trans. Computers, 1990

Scalable Shared-Memory Multiprocessor Architectures.
Computer, 1990

The Benefits of Global Dataflow Analysis for an Optimizing Prolog Compiler.
Proceedings of the Logic Programming, Proceedings of the 1990 North American Conference, Austin, Texas, USA, October 29, 1990

Fast Prolog with an Extended General Purpose Architecture.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

The Aquarius IIU System.
Proceedings of the First International Conference on Systems Integration, 1990

1988
A two-tier memory architecture for high-performance multiprocessor systems.
Proceedings of the 2nd international conference on Supercomputing, 1988

Prolog at Berkeley.
Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988

1987
Aquarius.
SIGARCH Comput. Archit. News, 1987

An Empirical Study of the Warren Abstract Machine.
Proceedings of the 1987 Symposium on Logic Programming, San Francisco, California, USA, August 31, 1987

Experience with Prolog as a Hardware Specification Language.
Proceedings of the 1987 Symposium on Logic Programming, San Francisco, California, USA, August 31, 1987

Performance Studies of a Parallel Prolog Architecture.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1986
Multiprocessor Cache Synchronization: Issues, Innovations, Evolution.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Delay reduction using simulated annealing.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation.
Proceedings of the Spring COMPCON'86, 1986

1985
Fast fourier transform processors using Gaussian residue arithmetic.
J. Parallel Distributed Comput., 1985

Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency Analysis.
Proceedings of the 1985 Symposium on Logic Programming, 1985

Compiling Prolog into microcode: a case study using the NCR/32-000.
Proceedings of the 18th annual workshop on Microprogramming, 1985

Performance Studies of a Prolog Machine Architecture.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

Aquarius - A High Performance Computing System for Symbolic/Numeric Applications.
Proceedings of the Spring COMPCON'85, 1985

AND-Parallelism of Logic Programs Based on a Static Data Dependency Analysis.
Proceedings of the Spring COMPCON'85, 1985

1984
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations.
IEEE Trans. Computers, 1984

Design decisions influencing the microarchitecture for a Prolog machine.
Proceedings of the 17th annual workshop on Microprogramming, 1984

The Aquarius Project.
Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1979
Very Fast Fourier Transform Algorithms Hardware for Implementation.
IEEE Trans. Computers, 1979

1978
X-Tree: A Tree Structured Multi-Processor Computer Architecture.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

Communication In X-TREE, A Modular Multiprocessor System.
Proceedings of the Proceedings 1978 ACM Annual Conference, 1978

1974
Fourier Transform Computers Using CORDIC Iterations.
IEEE Trans. Computers, 1974


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