Altamiro Amadeu Susin

Orcid: 0000-0001-7034-5336

Affiliations:
  • Federal University of Rio Grande do Sul (UFRGS), Computer Science Department, Brazil


According to our database1, Altamiro Amadeu Susin authored at least 159 papers between 1981 and 2023.

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Bibliography

2023
Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge Devices.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2021
A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images.
IEEE Geosci. Remote. Sens. Lett., 2021

2020
A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma-Delta Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Complexity and compression efficiency assessment of 3D-HEVC encoder.
Multim. Tools Appl., 2020

High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction.
IEEE Des. Test, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

2019
Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

2018
A Novel Resection-Intersection Algorithm With Fast Triangulation Applied to Monocular Visual Odometry.
IEEE Trans. Intell. Transp. Syst., 2018

A 0.6-V, 74.2-dB DR Continuous-Time Sigma-Delta Modulator With Inverter-Based Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Optimized Solution to Accelerate in Hardware an Intra H.264/SVC Video Encoder.
IEEE Micro, 2018

Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Reliability analysis on case-study traffic sign convolutional neural network on APSoC.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Wheat Plots Segmentation for Experimental Agricultural Field from Visible and Multispectral UAV Imaging.
Proceedings of the Intelligent Systems and Applications, 2018

A Framework for Automatic Recognition of Cell Damage on Microscopic Images using Artificial Neural Networks.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A P300 potential evaluation wavelet method comparing individuals with high and low risk for alcoholism.
Neural Comput. Appl., 2017

Models of computation for NoC mapping: Timing and energy saving awareness.
Microelectron. J., 2017

Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection.
Microprocess. Microsystems, 2017

Monocular Visual Odometry with Cyclic Estimation.
Proceedings of the 30th SIBGRAPI Conference on Graphics, Patterns and Images, 2017

Data compression and decompression Integrated Circuit for AC Power Quality data.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A digitally tunable 4th-order Gm-C low-pass filter for multi-standards receivers.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Thermal optimization using adaptive approximate computing for video coding.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A novel caching algorithm for VoD proxy implementation and its evaluation including a new set of metrics for efficiency analysis.
J. Braz. Comput. Soc., 2015

PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A third-order 1 MHz continuous-time sigma-delta modulator in a 130 nm CMOS process.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

High compression ratio algorithm for power quality signals.
Proceedings of the 24th IEEE International Symposium on Industrial Electronics, 2015

Performance evaluation of hierarchical NoC topologies for stacked 3D ICs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Adaptive Shared Memory Control for Multimedia Systems-on-Chip.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Ginga MiddleWare on a SoC for Digital Television Set-Top Box.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

TONE: adaptive temperature optimization for the next generation video encoders.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Adaptive multiple switching strategy toward an ideal NoC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Run-time SoC memory subsystem mapping of heterogeneous clients.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

H.264 8x8 inverse transform architecture optimization.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A NOC closed-loop performance monitor and adapter.
Microprocess. Microsystems, 2013

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.
J. Real Time Image Process., 2013

Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues.
Int. J. Reconfigurable Comput., 2013

A power-efficient hierarchical network-on-chip topology for stacked 3D ICs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013

Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulink.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Memory subsystem architecture design for multimedia applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfigurable Comput., 2012

Towards an Efficient Memory Architecture for Video Decoding Systems.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Namimote: A Low-Cost Sensor Node for Wireless Sensor Networks.
Proceedings of the Internet of Things, Smart Spaces, and Next Generation Networking, 2012

Floorplan-aware hierarchical NoC topology with GALS interfaces.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

2011
Reconfigurable Routers for Low Power and High Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2011

CAFES: A framework for intrachip application modeling and communication architecture design.
J. Parallel Distributed Comput., 2011

Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Efficient hardware solution for practical intra h.264/SVC video encoder implementation.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

Embedded sensor system and techniques to evaluate the comfort in public transportation.
Proceedings of the 14th International IEEE Conference on Intelligent Transportation Systems, 2011

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

High performance H.264/AVC encoding motion prediction algorithm.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

2010
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Hardware integrated quantization solution for improvement of computational H.264 encoder module.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Monitor-adapter coupling for NOC performance tuning.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Proposal of an improved motion estimation module for SVC.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Highly efficient forward two-dimensional DCT module architecture for H.264/SVC.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Practical analysis and refinement of a SVC standard scalable vídeo coder.
Proceedings of the XV Brazilian Symposium on Multimedia and the Web, 2009

High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A High Performance H.264 Deblocking Filter.
Proceedings of the Advances in Image and Video Technology, Third Pacific Rim Symposium, 2009

Adaptive router architecture based on traffic behavior observability.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

NoC Power Optimization Using a Reconfigurable Router.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

The Need for Reconfigurable Routers in Networks-on-Chip.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A new march sequence to fit DDR SDRAM test in burst mode.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A wide band CMOS differential voltage-controlled ring oscillator.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high throughput and low cost diamond search architecture for HDTV motion estimation.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
Design and FPGA Prototyping of a H.264/AVC Main Profile.
J. Braz. Comput. Soc., 2007

Reducing Test Time Using an Enhanced RF Loopback.
J. Electron. Test., 2007

RF Digital Signal Generation Beyond Nyquist.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

An HDTV H.264 deblocking filter in FPGA with RGB video output.
Proceedings of the IFIP VLSI-SoC 2007, 2007

3D Atlas Building in the Context of Head and Neck Radiotherapy Based on Dense Deformation Fields.
Proceedings of the SIBGRAPI 2007, 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Motion Compensation Hardware Accelerator Architecture for H.264/AVC.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

Non-rigid registration methods assessment of 3D CT images for head-neck radiotherapy.
Proceedings of the Medical Imaging 2007: Image Processing, 2007

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Quality Assessment of Non-Rigid Registration Methods for Atlas-Based Segmentation in Head-Neck Radiotherapy.
Proceedings of the IEEE International Conference on Acoustics, 2007

Digital Generation of Signals for Low Cost RF BIST.
Proceedings of the 12th European Test Symposium, 2007

2006
Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Automatic generation of neural networks for image processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable communications for image processing applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Contextual Resources use: a Proof of Concept through the APACHES' Platform.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

An improved RF loopback for test time reduction.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Low Cost On-Line Testing Strategy for RF Circuits.
J. Electron. Test., 2005

Low Cost BIST for Static and Dynamic Testing of ADCs.
J. Electron. Test., 2005

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Models for Embedded Application Mapping onto NoCs: Timing Analysis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Energy and latency evaluation of NoC topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Gradient pile up for edge detection on hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design space exploration on heterogeneous network-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Noise Figure Evaluation Using Low Cost BIST.
Proceedings of the 2005 Design, 2005

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.
Proceedings of the 2005 Design, 2005

ERP signal identification of Individuals at Risk for Alcoholism using Learning Vector Quantization Network.
Proceedings of the 2005 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2005

Time and energy efficient mapping of embedded applications onto NoCs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
INL and DNL estimation based on noise for ADC test.
IEEE Trans. Instrum. Meas., 2004

ParIS: a parameterizable interconnect switch for networks-on-chip.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Abstract RTOS Modeling for Embedded Systems.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

A comparison of totally digital ADCs for SOCs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low Cost On-Line Testing of RF Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Gradient Pile up Algorithm for Edge Enhancement and Detection.
Proceedings of the Image Analysis and Recognition: International Conference, 2004

Towards a BIST technique for noise figure evaluation.
Proceedings of the 9th European Test Symposium, 2004

RASoC: A Router Soft-Core for Networks-on-Chip.
Proceedings of the 2004 Design, 2004

Low Cost Analog Testing of RF Signal Paths.
Proceedings of the 2004 Design, 2004

Classification of event-related potentials in individuals at risk for alcoholism using wavelet transform and artificial neural network.
Proceedings of the 2004 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2004

2003
Testing analog circuits using spectral analysis.
Microelectron. J., 2003

A Statistical Sampler for a New On-Line Analog Test Method.
J. Electron. Test., 2003

Ultra Low Cost Analog BIST Using Spectral Analysis.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

The Impact of NoC Reuse on the Testing of Core-based Systems.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

SoCIN: A Parametric and Scalable Network-on-Chip.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Testing RF Signal Paths Using Spectral Analysis and Subsampling.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Ultimate low cost analog BIST.
Proceedings of the 40th Design Automation Conference, 2003

2002
A Study on Communication Issues for Systems-on-Chip.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Analysis and Implementation of a Stochastic Multiplier for Electrical Power Measurement.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A Statistical Sampler for Increasing Analog Circuits Observability.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A Noise Generator for Analog-to-Digital Converter Testing.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Complex Adaptive Signal Processing for Analog Testing.
Proceedings of the 3rd Latin American Test Workshop, 2002

2001
Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S.
RITA, 2001

Communication Architectures for System-on-Chip.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
A New Automatic Circular Decomposition Algorithm Applied to Blood Cells Image.
Proceedings of the 1st IEEE International Symposium on Bioinformatics and Biomedical Engineering, 2000

1997
F-Timer: dedicated FPGA to real-time systems design support.
Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, 1997

1996
Prototyping and reengineering of microcontroller-based systems.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Embedded Systems Design with Frontend Compilers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

System Design using ASIPs.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

1994
Algorithms and architectures to computational systems implementation.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

1993
SHC-SLX: A levelized compiled, event driven interpreted VLSI simulator.
Microprocess. Microprogramming, 1993

1981
Etude des parties opératives à éléments modulaires pour processeurs monolithiques.
PhD thesis, 1981


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