Almudena Lindoso

Orcid: 0000-0001-5870-6493

According to our database1, Almudena Lindoso authored at least 25 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs.
J. Supercomput., June, 2024

Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs.
IEEE Trans. Aerosp. Electron. Syst., 2024

Analysing the radiation reliability, performance and energy consumption of low-power SoC through heterogeneous parallelism.
Sustain. Comput. Informatics Syst., 2024

2023
Hybrid CPU-GPU implementation of the transformed spatial domain channel estimation algorithm for mmWave MIMO systems.
J. Supercomput., June, 2023

Formal Verification of Fault-Tolerant Hardware Designs.
IEEE Access, 2023

Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors.
IEEE Access, 2023

2022
Performance analysis of a millimeter wave MIMO channel estimation method in an embedded multi-core processor.
J. Supercomput., 2022

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique.
IEEE Access, 2022

Acceleration of the TSDCE MIMO Channel Estimation Algorithm on a Multi-core Platform.
Proceedings of the EATIS 2022: 11th Euro American Conference on Telematics and Information Systems, Aveiro, Portugal, June 1, 2022

2021
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC.
J. Supercomput., 2021

2020
Evaluation of a Reduced Precision Redundancy FFT Design.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2018
PTM-based hybrid error-detection architecture for ARM microprocessors.
Microelectron. Reliab., 2018

2016
A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications.
IEEE Trans. Dependable Secur. Comput., 2016

Online Test of Control Flow Errors: A New Debug Interface-Based Approach.
IEEE Trans. Computers, 2016

2014
A new solution to on-line detection of Control Flow Errors.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Exploiting the debug interface to support on-line test of control flow errors.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection.
IEEE Trans. Computers, 2012

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.
J. Electron. Test., 2012

2011
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.
Proceedings of the 12th Latin American Test Workshop, 2011

2008
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.
Proceedings of the FPL 2008, 2008

2007
High performance FPGA-based image correlation.
J. Real Time Image Process., 2007

Correlation-Based Fingerprint Matching with Orientation Field Alignment.
Proceedings of the Advances in Biometrics, International Conference, 2007

Wavelet-Based Fingerprint Region Selection.
Proceedings of the Computer Analysis of Images and Patterns, 12th International Conference, 2007

2006
FPGA implementation for an iris biometric processor.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
Correlation-Based Fingerprint Matching Using FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005


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