Allon Adir
Orcid: 0000-0001-8128-6706
According to our database1,
Allon Adir
authored at least 31 papers
between 2001 and 2023.
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Bibliography
2023
Proc. Priv. Enhancing Technol., January, 2023
ELECTRON: An Architectural Framework for Securing the Smart Electrical Grid with Federated Detection, Dynamic Risk Assessment and Self-Healing.
Proceedings of the 18th International Conference on Availability, Reliability and Security, 2023
2022
Privacy-Preserving Record Linkage Using Local Sensitive Hash and Private Set Intersection.
Proceedings of the Applied Cryptography and Network Security Workshops, 2022
2020
Tile Tensors: A versatile data structure with descriptive shapes for homomorphic encryption.
CoRR, 2020
Proceedings of the Cyber-Physical Security for Critical Infrastructures Protection, 2020
2017
Proceedings of the 10th ACM International Systems and Storage Conference, 2017
Proceedings of the 33rd IEEE International Conference on Data Engineering, 2017
2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Proceedings of the Hardware and Software: Verification and Testing, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A New Test-Generation Methodology for System-Level Verification of Production Processes.
Proceedings of the Hardware and Software: Verification and Testing, 2012
2011
Proceedings of the Hardware and Software: Verification and Testing, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
Proceedings of the Hardware and Software: Verification and Testing, 2010
Proceedings of the Hardware and Software: Verification and Testing, 2010
2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Des. Test Comput., 2004
2003
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture.
IEEE Trans. Parallel Distributed Syst., 2003
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
2002
Generating concurrent test-programs with collisions for multi-processor verification.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001