Allon Adir

Orcid: 0000-0001-8128-6706

According to our database1, Allon Adir authored at least 31 papers between 2001 and 2023.

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Bibliography

2023
HeLayers: A Tile Tensors Framework for Large Neural Networks on Encrypted Data.
Proc. Priv. Enhancing Technol., January, 2023


2022
Privacy-Preserving Record Linkage Using Local Sensitive Hash and Private Set Intersection.
Proceedings of the Applied Cryptography and Network Security Workshops, 2022

2020
Tile Tensors: A versatile data structure with descriptive shapes for homomorphic encryption.
CoRR, 2020

A Cloud-Based Anomaly Detection for IoT Big Data.
Proceedings of the Cyber-Physical Security for Critical Infrastructures Protection, 2020

2017
Big data analysis of cloud storage logs using spark.
Proceedings of the 10th ACM International Systems and Storage Conference, 2017

Anomaly Detection in Large Databases Using Behavioral Patterning.
Proceedings of the 33rd IEEE International Conference on Data Engineering, 2017

2014

Using a High-Level Test Generation Expert System for Testing In-Car Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Dynamic Selection of Trace Signals for Post-Silicon Debug.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Development and Verification of Complex Hybrid Systems Using Synthesizable Monitors.
Proceedings of the Hardware and Software: Verification and Testing, 2013

2012
Concurrent Generation of Concurrent Programs for Post-Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A New Test-Generation Methodology for System-Level Verification of Production Processes.
Proceedings of the Hardware and Software: Verification and Testing, 2012

2011
Dynamic Test Data Generation for Data Intensive Applications.
Proceedings of the Hardware and Software: Verification and Testing, 2011

A unified methodology for pre-silicon verification and post-silicon validation.
Proceedings of the Design, Automation and Test in Europe, 2011

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor.
Proceedings of the 48th Design Automation Conference, 2011

Threadmill: a post-silicon exerciser for multi-threaded processors.
Proceedings of the 48th Design Automation Conference, 2011

2010
Advances in Simultaneous Multithreading Testcase Generation Methods.
Proceedings of the Hardware and Software: Verification and Testing, 2010

Reaching Coverage Closure in Post-silicon Validation.
Proceedings of the Hardware and Software: Verification and Testing, 2010

2007
A Framework for the Validation of Processor Architecture Compliance.
Proceedings of the 44th Design Automation Conference, 2007

2006
Addressing Test Generation Challenges for Configurable Processor Verification.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
VLIW: a case study of parallelism verification.
Proceedings of the 42nd Design Automation Conference, 2005

A generic micro-architectural test plan approach for microprocessor verification.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Des. Test Comput., 2004

2003
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture.
IEEE Trans. Parallel Distributed Syst., 2003

DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Piparazzi: a test program generator for micro-architecture flow verification.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002
Generating concurrent test-programs with collisions for multi-processor verification.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Adaptive test program generation: planning for the unplanned.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Improving test quality through resource reallocation.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001


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