Alireza Tajary

According to our database1, Alireza Tajary authored at least 13 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A novel deep neural network structure for software fault prediction.
PeerJ Comput. Sci., 2024

2023
Persian printed text line detection based on font size.
Multim. Tools Appl., 2023

Game-based congestion-aware routing algorithm in wireless network on chips.
Int. J. Ad Hoc Ubiquitous Comput., 2023

2020
IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes.
Microprocess. Microsystems, 2020

Scalable THz Network-On-Chip Architecture for Multichip Systems.
J. Comput. Networks Commun., 2020

Printed Persian OCR system using deep learning.
IET Image Process., 2020

2016
Using instruction result locality and re-execution to mitigate silent data corruptions.
Microelectron. Reliab., 2016

A Metallic CNT Tolerant Design Methodology for Carbon Nanotube-Based Programmable Gate Arrays.
J. Circuits Syst. Comput., 2016

An Efficient Soft Error Detection in Multicore Processors Running Server Applications.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2011
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors.
Des. Autom. Embed. Syst., 2011

CPU-aware, process-level redundancy to tolerate faults in multi-core.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

2010
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010


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