Alireza Shafaei
According to our database1,
Alireza Shafaei
authored at least 36 papers
between 2010 and 2021.
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Bibliography
2021
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021
2019
Proceedings of the 30th British Machine Vision Conference 2019, 2019
2018
Does Your Model Know the Digit 6 Is Not a Cat? A Less Biased Evaluation of "Outlier" Detectors.
CoRR, 2018
MASAGA: A Linearly-Convergent Stochastic First-Order Method for Optimization on Manifolds.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Gate-all-around FET based 6T SRAM design using a device-circuit co-optimization framework.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Design of multiple fanout clock distribution network for rapid single flux quantum technology.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Quantum Inf. Comput., 2016
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 13th Conference on Computer and Robot Vision, 2016
Proceedings of the British Machine Vision Conference 2016, 2016
2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits.
Quantum Inf. Process., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the British Machine Vision Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the Reversible Computation - 5th International Conference, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2011
An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC.
Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2011
2010
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010