Alireza Khalafi

According to our database, Alireza Khalafi authored at least 4 papers between 1999 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture.

David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht

SIGARCH Comput. Archit. News, 2003

Levo - A Scalable Processor With High IPC.

Augustus K. Uht, David Morano, Alireza Khalafi, David R. Kaeli

J. Instr. Level Parallelism, 2003

2002

Realizing High IPC Using Time-Tagged Resource-Flow Computing.

Augustus K. Uht, Alireza Khalafi, David Morano, Marcos de Alba, David R. Kaeli

Proceedings of the Euro-Par 2002, 2002

1999

Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance.

John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis

IEEE Trans. Computers, 1999