Alin Razafindraibe

According to our database, Alin Razafindraibe authored at least 11 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2011

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback

Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin

CoRR, 2011

2008

Physical Design of FPGA Interconnect to Prevent Information Leakage.

Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Improvement of dual rail logic as a countermeasure against DPA.

Alin Razafindraibe, Michel Robert, Philippe Maurine

Proceedings of the IFIP VLSI-SoC 2007, 2007

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.

Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.

Alin Razafindraibe, Michel Robert, Philippe Maurine

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates.

Alin Razafindraibe, Philippe Maurine

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Novel Asynchronous e-FPGA Architecture for Security Applications.

Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006

Security evaluation of dual rail logic against DPA attacks.

Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin

Proceedings of the IFIP VLSI-SoC 2006, 2006

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.

Alin Razafindraibe, Michel Robert, Philippe Maurine

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

Compact and Secured Primitives for the Design of Asynchronous Circuits.

Alin Razafindraibe, Michel Robert, Philippe Maurine

J. Low Power Electron., 2005

A Method to Design Compact Dual-rail Asynchronous Primitives.

Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine

Proceedings of the Integrated Circuit and System Design, 2005