Ali Sheikholeslami

IEEE J. Solid State Circuits, July, 2024

Graph clustering with Boltzmann machines.

[BibT_eX]

[DOI]

Pierre Miasnikof

Mohammad Bagherbeik

Discret. Appl. Math., January, 2024

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI.

[BibT_eX]

[DOI]

Jhoan Salinas

IEEE Open J. Circuits Syst., 2024

Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication.

[BibT_eX]

[DOI]

Mohammad Emami Meybodi

IEEE Open J. Circuits Syst., 2024

A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers.

[BibT_eX]

[DOI]

Miad Laghaei

IEEE Open J. Circuits Syst., 2024

FBMC vs. PAM and DMT for High-Speed Wireline Communication.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2024

2023

Optimization via Rejection-Free Partial Neighbor Search.

[BibT_eX]

[DOI]

Stat. Comput., December, 2023

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2023

A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE).

[BibT_eX]

[DOI]

Mohammad Emami Meybodi

IEEE Open J. Circuits Syst., 2022

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2022

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications.

[BibT_eX]

[DOI]

Jeremy Cosson-Martin

IEEE Open J. Circuits Syst., 2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications.

[BibT_eX]

[DOI]

Jeremy Cosson-Martin

IEEE Open J. Circuits Syst., 2021

Jump Markov chains and rejection-free Metropolis algorithms.

[BibT_eX]

[DOI]

Comput. Stat., 2021

The Power of Parallelism in Stochastic Search for Global Optimum: Keynote Paper.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

Caching and Vectorization Schemes to Accelerate Local Search Algorithms for Assignment Problems.

[BibT_eX]

[DOI]

Mohammad Bagherbeik

Proceedings of the IEEE Congress on Evolutionary Computation, 2021

2020

Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial.

[BibT_eX]

[DOI]

Keivan Dabiri

Mehrdad Malekmohammadi

IEEE Trans. Parallel Distributed Syst., 2020

A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.

[BibT_eX]

[DOI]

Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020

Keynote II: Digital Annealer: A Stochastic Search for Global Optimum.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

A Hamiltonian Engine for Radiotherapy Optimization.

[BibT_eX]

[DOI]

Mehrdad Malekmohammadi

Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019

A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security.

[BibT_eX]

[DOI]

Mohammad Javad-Kalbasi

Keivan Dabiri

Shahrokh Valaee

Proceedings of the IEEE International Conference on Acoustics, 2019

A 30Gb/s 2x Half-Baud-Rate CDR.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

2017

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Tutorials.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine.

[BibT_eX]

[DOI]

Behraz Vatankhahghadim

Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

Jitter injection for on-chip jitter measurement in PI-based CDRs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Low-Swing Signaling for FPGA Power Reduction (Abstract Only).

[BibT_eX]

[DOI]

Sayeh Sharifymoghaddam

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA.

[BibT_eX]

[DOI]

Aynaz Vatankhahghadim

W. Song

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 3x blind ADC-based CDR for a 20 dB loss channel.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.

[BibT_eX]

[DOI]

Joshua Liang

IEEE J. Solid State Circuits, 2015

A Reference-Less Single-Loop Half-Rate Binary CDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Aynaz Vatankhahghadim

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions.

[BibT_eX]

[DOI]

Aynaz Vatankhahghadim

Safeen Huda

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".

[BibT_eX]

[DOI]

Ravi Shivnaraine

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.

[BibT_eX]

[DOI]

Joshua Liang

Proceedings of the Symposium on VLSI Circuits, 2014

29.2 A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.

[BibT_eX]

[DOI]

Clifford Ting

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Novel STT-MRAM Cell With Disturbance-Free Read Operation.

[BibT_eX]

[DOI]

Safeen Huda

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Blind Baud-Rate ADC-Based CDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Design metrics for blind ADC-based wireline receivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

10-40 Gb/s I/O design for data communications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

High-speed transceivers: Standards, challenges, and future.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A pattern-guided adaptive equalizer in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A predictive current control method for shunt active filter with windowing based wavelet transform in harmonic detection.

[BibT_eX]

[DOI]

Khalil Gorgani Firouzjah

Mohammad Reza Karami Mollaei

F. Heydari

Simul. Model. Pract. Theory, 2009

A current independent method based on synchronized voltage measurement for fault location on transmission lines.

[BibT_eX]

[DOI]

Khalil Gorgani Firouzjah

Simul. Model. Pract. Theory, 2009

Will ADCs overtake binary frontends in backplane signaling?

[BibT_eX]

[DOI]

Robert Payne

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial).

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

2008

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM).

[BibT_eX]

[DOI]

Oleksiy Tyshchenko

IEEE J. Solid State Circuits, 2008

2007

Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2007

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

2006

An area-efficient universal cryptography processor for smart cards.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Real-time face detection and lip feature extraction using field-programmable gate arrays.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part B, 2006

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A 3.2Gb/s Semi-Blind-Oversampling CDR.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Robust sound localization in 0.18 µm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2005

Real-time dual-microphone speech enhancement using field programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Using cache to reduce power in content-addressable memories (CAMs).

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling.

[BibT_eX]

[DOI]

Marcus van Ierssel

Joyce Wong

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Hardware implementation perspectives of digital video watermarking algorithms.

[BibT_eX]

[DOI]

Nebu John Mathai

Deepa Kundur

IEEE Trans. Signal Process., 2003

Introduction: Special Issue in Recognition of Kenneth C. Smith.

[BibT_eX]

D. Michael Miller

J. Multiple Valued Log. Soft Comput., 2003

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC].

[BibT_eX]

[DOI]

Simon Segars

Stephen Fischer

IEEE J. Solid State Circuits, 2003

A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories.

[BibT_eX]

[DOI]

Igor Arsovski

IEEE J. Solid State Circuits, 2003

A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme.

[BibT_eX]

[DOI]

Igor Arsovski

Trevis Chandler

IEEE J. Solid State Circuits, 2003

VLSI implementation of a real-time video watermark embedder and detector.

[BibT_eX]

[DOI]

Nebu John Muthui

Deepa Kundur

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Signaling capacity of FR4 PCB traces for chip-to-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Real-time sound localization using field-programmable gate arrays.

[BibT_eX]

[DOI]

Duy Cuong Nguyen

Parham Aarabi

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A 16 kb 1T1C FeRAM test chip using current-based reference scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

A survey of circuit innovations in ferroelectric random-access memories.

[BibT_eX]

[DOI]

P. Glenn Gulak

Proc. IEEE, 2000

1998

Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic.

[BibT_eX]

[DOI]

R. Yoshimura

P. Glenn Gulak

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1996

A Multiple-Valued Ferroelectric Content-Addressable Memory.

[BibT_eX]

[DOI]