Ali Sheikholeslami
Orcid: 0000-0003-0970-6897
According to our database1,
Ali Sheikholeslami
authored at least 95 papers
between 1996 and 2024.
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Bibliography
2024
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process.
IEEE J. Solid State Circuits, July, 2024
Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication.
IEEE Open J. Circuits Syst., 2024
IEEE Open J. Circuits Syst., 2024
2023
Stat. Comput., December, 2023
An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process.
IEEE Open J. Circuits Syst., 2023
A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE).
IEEE Open J. Circuits Syst., 2022
A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier.
IEEE Open J. Circuits Syst., 2022
IEEE Open J. Circuits Syst., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
2021
Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication.
IEEE Open J. Circuits Syst., 2021
Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications.
IEEE Open J. Circuits Syst., 2021
Proceedings of the 47th ESSCIRC 2021, 2021
Caching and Vectorization Schemes to Accelerate Local Search Algorithms for Assignment Problems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2021
2020
Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial.
IEEE Trans. Parallel Distributed Syst., 2020
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.
Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
2017
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
2015
A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE J. Solid State Circuits, 2014
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A predictive current control method for shunt active filter with windowing based wavelet transform in harmonic detection.
Simul. Model. Pract. Theory, 2009
A current independent method based on synchronized voltage measurement for fault location on transmission lines.
Simul. Model. Pract. Theory, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the ISMVL 2009, 2009
2008
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE J. Solid State Circuits, 2008
2007
IEEE Trans. Signal Process., 2007
IEEE J. Solid State Circuits, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Real-time face detection and lip feature extraction using field-programmable gate arrays.
IEEE Trans. Syst. Man Cybern. Part B, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme.
IEEE J. Solid State Circuits, 2004
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM).
IEEE J. Solid State Circuits, 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
2003
IEEE Trans. Signal Process., 2003
Introduction: Special Issue in Recognition of Kenneth C. Smith.
J. Multiple Valued Log. Soft Comput., 2003
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories.
IEEE J. Solid State Circuits, 2003
Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC].
IEEE J. Solid State Circuits, 2003
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories.
IEEE J. Solid State Circuits, 2003
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme.
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2000
Proc. IEEE, 2000
1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996