Ali Keshavarzi

Orcid: 0000-0001-6938-1161

According to our database1, Ali Keshavarzi authored at least 43 papers between 1997 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Towards site-specific management of soil organic carbon: Comparing support vector machine and ordinary kriging approaches based on pedo-geomorphometric factors.
Comput. Electron. Agric., January, 2024

Few-Shot Airway-Tree Modeling Using Data-Driven Sparse Priors.
Proceedings of the IEEE International Symposium on Biomedical Imaging, 2024

2021
Dealing with soil organic carbon modeling: some insights from an agro-ecosystem in Northeast Iran.
Earth Sci. Informatics, 2021

2020
FerroElectronics for Edge Intelligence.
IEEE Micro, 2020

2019
Edge Intelligence - On the Challenging Road to a Trillion Smart Connected IoT Devices.
IEEE Des. Test, 2019

Determining the best ISUM (Improved stock unearthing Method) sampling point number to model long-term soil transport and micro-topographical changes in vineyards.
Comput. Electron. Agric., 2019

2017
Using soil easily measured parameters for estimating soil water capacity: Soft computing approaches.
Comput. Electron. Agric., 2017

Modeling soil cation exchange capacity using soil parameters: Assessing the heuristic models.
Comput. Electron. Agric., 2017

2014
Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
EP3: Empowering the killer SoC applications of 2020.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Developing Pedotransfer Functions for Estimating Field Capacity and Permanent Wilting Point Using Fuzzy Table Look-up Scheme.
Comput. Inf. Sci., 2011

2009
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits, 2009

2008
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
Impact of Thermal Gradients on Clock Skew and Testing.
IEEE Des. Test Comput., 2006

2005
Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs.
Proceedings of the 2005 Design, 2005

2004
DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Des. Test Comput., 2004

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Design optimizations for microprocessors at low temperature.
Proceedings of the 41th Design Automation Conference, 2004

2003
Multiple-parameter CMOS IC testing with increased sensitivity for I<sub>DDQ</sub>.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Forward body bias for microprocessors in 130-nm technology generation and beyond.
IEEE J. Solid State Circuits, 2003

Burn-in Temperature Projections for Deep Sub-micron Technologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Thermal Management of High Performance Microprocessors.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Parameter variations and impact on circuits and microarchitecture.
Proceedings of the 40th Design Automation Conference, 2003

CMOS IC nanometer technology failure mechanisms.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Des. Test Comput., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Des. Test Comput., 2002

Challenges in Nanometric Technology Scaling: Trends and Projections.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Parametric Failures in CMOS ICs - A Defect-Based Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Design and Test of Low Voltage CMOS Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1997
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997


  Loading...