Ali Jahanian
Orcid: 0000-0003-2292-4135Affiliations:
- Shahid Beheshti University, Tehran, Iran
- Amirkabir University of Technology, Tehran, Iran (PhD 2007)
According to our database1,
Ali Jahanian
authored at least 61 papers
between 2004 and 2024.
Collaborative distances:
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Bibliography
2024
J. Circuits Syst. Comput., February, 2024
2023
Generic and scalable DNA-based logic design methodology for massive parallel computation.
J. Supercomput., 2023
2022
Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process.
J. Supercomput., 2022
Accurate Crosstalk Noise Modeling and Analysis of Non-Identical Lossy Interconnections Using Convex Optimization Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ISC Int. J. Inf. Secur., 2022
Flexible and Automatable Microfluidic-based Architecture and CAD Algorithm for Implementation of Large DNA Digital Storage.
Proceedings of the 27th International Computer Conference, Computer Society of Iran, 2022
2021
Intensive Analysis of Physical Parameters of Power Sensors for Remote Side-Channel Attacks.
ISC Int. J. Inf. Secur., 2021
2020
Low-Cost Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip.
CoRR, 2020
A Cost & Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip.
CoRR, 2020
Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Analysis of Geometrical Parameters for Remote Side-Channel Attacks on Multi-Tenant FPGAs.
Proceedings of the 17th International ISC Conference on Information Security and Cryptology, 2020
Cost-Effective and Practical Countermeasure against the Template Side Channel Attack.
Proceedings of the 17th International ISC Conference on Information Security and Cryptology, 2020
2018
Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation.
Microprocess. Microsystems, 2018
Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018
2017
DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design.
IEEE Trans. Biomed. Circuits Syst., 2017
J. Circuits Syst. Comput., 2017
Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area.
J. Circuits Syst. Comput., 2017
Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation.
Proceedings of the Euromicro Conference on Digital System Design, 2017
Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology.
Microprocess. Microsystems, 2016
ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow.
ISC Int. J. Inf. Secur., 2016
Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose.
ISC Int. J. Inf. Secur., 2016
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering.
J. Electron. Test., 2016
Security improvement of FPGA configuration file against the reverse engineering attack.
Proceedings of the 13th International Iranian Society of Cryptology Conference on Information Security and Cryptology, 2016
2015
A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform.
J. Supercomput., 2015
Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability.
ISC Int. J. Inf. Secur., 2015
Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage.
Integr., 2015
2014
Improved delay and Process variation Tolerant Clock Tree Network in ultra-Large Circuits using Hybrid RF/metal Clock Routing.
J. Circuits Syst. Comput., 2014
Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs.
Integr., 2014
Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
2013
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
2012
Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects.
IEICE Trans. Electron., 2012
Improved timing closure by analytical buffer and TSV planning in three-dimensional chips.
IEICE Electron. Express, 2012
Comput. Electr. Eng., 2012
Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments.
Proceedings of the ICAART 2012 - Proceedings of the 4th International Conference on Agents and Artificial Intelligence, Volume 2, 2012
Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology.
Integr., 2011
Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation.
IEICE Electron. Express, 2011
A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
J. Circuits Syst. Comput., 2010
2009
Int. J. Inf. Acquis., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Using metro-on-chip in physical design flow for congestion and routability improvement.
Microelectron. J., 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
IEICE Electron. Express, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004