Ali Farhang

According to our database, Ali Farhang authored at least 3 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

A 256-Kb Dual-V_CC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

IEEE J. Solid State Circuits, 2007

2006

A 4.2GHz 0.3mm2 256kb Dual-V_cc SRAM Building Block in 65nm CMOS.

Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

A 6-GHz 16-kB L1 cache in a 100-nm dual-V_T technology using a bitline leakage reduction (BLR) technique.

Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De

IEEE J. Solid State Circuits, 2003