Ali Farhang
According to our database1,
Ali Farhang
authored at least 3 papers
between 2003 and 2007.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2007
A 256-Kb Dual-V<sub>CC</sub> SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
IEEE J. Solid State Circuits, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2003
A 6-GHz 16-kB L1 cache in a 100-nm dual-V<sub>T</sub> technology using a bitline leakage reduction (BLR) technique.
IEEE J. Solid State Circuits, 2003