Ali Azarpeyvand

Orcid: 0000-0002-4166-7528

According to our database1, Ali Azarpeyvand authored at least 24 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Publisher Correction: Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation.
J. Supercomput., June, 2024

Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation.
J. Supercomput., May, 2024

Automatic High Functional Coverage Stimuli Generation for Assertion-based Verification.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators.
Proceedings of the IEEE European Test Symposium, 2024

Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023
A Comprehensive Survey on Model Quantization for Deep Neural Networks in Image Classification.
ACM Trans. Intell. Syst. Technol., December, 2023

Propounding First Artificial Intelligence Approach for Predicting Robbery Behavior Potential in an Indoor Security Camera.
IEEE Access, 2023

2022
Data-Driven and Knowledge-Based Algorithms for Gene Network Reconstruction on High-Dimensional Data.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Logarithm-approximate floating-point multiplier.
Microelectron. J., 2022

A Comprehensive Survey on Model Quantization for Deep Neural Networks.
CoRR, 2022

2021
Significantly improving human detection in low-resolution images by retraining YOLOv3.
Proceedings of the 26th International Computer Conference, Computer Society of Iran, 2021

2018
Code Acceleration Using Memristor-Based Approximate Matrix Multiplier: Application to Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.
J. Electron. Test., 2018

2016
Reliability aware throughput management of chip multi-processor architecture via thread migration.
J. Supercomput., 2016

Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor.
Microprocess. Microsystems, 2016

An ultra-fast multi-objective optimization algorithm for VLIW architecture.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation.
IET Comput. Digit. Tech., 2015

2014
An analytical method for reliability aware instruction set extension.
J. Supercomput., 2014

2013
Reliability-aware cross-layer custom instruction screening.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Adaptive fault-tolerant DVFS with dynamic online AVF prediction.
Microelectron. Reliab., 2012

Vulnerability Analysis for Custom Instructions.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

CIVA: Custom instruction vulnerability analysis framework.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2010
Instruction reliability analysis for embedded processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2000
A novel architecture for sine-output direct digital frequency synthesizers using parabolic approximation.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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