Alfio Dario Grasso

Orcid: 0000-0002-5707-9683

Affiliations:
  • University of Catania, Italy


According to our database1, Alfio Dario Grasso authored at least 98 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A High Efficiency and High Power Density Active AC/DC Converter for Battery-Less US-Powered IMDs in a 28-nm CMOS Technology.
IEEE Access, 2024

Hybrid Cascode Compensation With Hybrid Q-Factor Control for Three-Stage Unconditionally Stable Amplifiers.
IEEE Access, 2024

Offset Compensation for Differential Charge-Based Capacitance Measurement.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C<sub>L</sub>.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A Novel Digital OTA Topology With 66-dB DC Gain and 12.3-kHz Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

A 0.3-V 8.5-μ a Bulk-Driven OTA.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Very-Low-Voltage Charge Pump Topologies for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Demystifying Regulating Active Rectifiers for Energy Harvesting Systems: A Tutorial Assisted by Verilog-A Models.
IEEE Access, 2023

A compensation scheme for three-stage OTAs with no Miller capacitors.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 28-nm, 0.5-V, 78.5-nA Switched Capacitor Current Reference with Active Trimming for sub-1V Implantable Medical Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

GBW Optimization in Two-Stage OTAs Operating in Weak Inversion.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

The Dickson Charge Pump as a Signal Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review.
Int. J. Circuit Theory Appl., 2022

Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach.
IEEE Access, 2022

A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers.
IEEE Access, 2022

A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology.
IEEE Access, 2022

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers.
IEEE Access, 2022

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range.
IEEE Access, 2022

A Design Procedure for Sizing Comparators in Active Rectifiers using $g_{m}/I_{D}$ Technique.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

A 0.63 pJ/bit Fully-Digital BPSK Demodulator for US-powered IMDs downlink in a 28-nm bulk CMOS technology.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Planar Capacitive Transducers for a Miniaturized Particulate Matter Detector.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

2021
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Time-Based Electronic Front-End for a Capacitive Particle Matter Detector.
Sensors, 2021

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes.
IEEE Access, 2021

Dickson Charge Pump: Design Strategy for Optimum Efficiency.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

An Efficient AC-DC Converter in 28nm Si-Bulk CMOS Technology for Piezo-Powered Medical Implanted Devices.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

28-nm CMOS Resistor-Less Voltage Reference with Process Corner Compensation.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
A Compact Temperature Sensor With a Resolution FoM of 1.82 pJ·K<sup>2</sup>.
IEEE Trans. Instrum. Meas., 2020

Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging.
IEEE Trans. Circuits Syst., 2020

A High-Performance Charge Pump Topology for Very-Low-Voltage Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Linear distribution of capacitance in Dickson charge pumps to reduce rise time.
Int. J. Circuit Theory Appl., 2020

Current-mode body-biased switch to increase performance of linear charge pumps.
Int. J. Circuit Theory Appl., 2020

A simple and effective design strategy to increase power conversion efficiency of linear charge pumps.
Int. J. Circuit Theory Appl., 2020

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor.
Int. J. Circuit Theory Appl., 2020

Sub-Femto-Farad Resolution Electronic Interfaces for Integrated Capacitive Sensors: A Review.
IEEE Access, 2020

A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start.
IEEE Access, 2020

2019
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Active load with cross-coupled bulk for high-gain high-CMRR nanometer CMOS differential stages.
Int. J. Circuit Theory Appl., 2019

Integrated Airborne Particle Matter Detector.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

CMOS Differential Stage with Improved DC Gain, CMRR and PSRR Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of C<sub>L</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Ultra-Low Power Amplifiers for IoT Nodes.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Clock Boosted Charge Pump with Reduced Rise Time.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation.
Int. J. Circuit Theory Appl., 2017

A toolbox for the symbolic analysis and simulation of linear analog circuits.
Proceedings of the 14th International Conference on Synthesis, 2017

Novel straightforward and effective extraction methodology for SiPM model parameters.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Area-optimized sub-fF offset trimming circuit for capacitive MEMS interfaces.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Symbolic factorization methodology for multistage amplifier transfer functions.
Int. J. Circuit Theory Appl., 2016

CMOS Non-tailed differential pair.
Int. J. Circuit Theory Appl., 2016

A 0.003-mm<sup>2</sup> 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Enhanced analytical model and output dynamic response of SiPM-Based electronic read-outs.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes.
IEEE Trans. Instrum. Meas., 2015

High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

0.7-V bulk-driven three-stage class-AB OTA.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Single-miller all-passive compensation network for three-stage OTAs.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A new accurate analytical expression for the SiPM transient response to single photons.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

High-performance frequency compensation topology for four-stage OTAs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Monolithic quenching-and-reset circuit for single-photon avalanche diodes.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Estimation of in-cylinder pressure using spark plug discharge current measurements.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Optimized frequency compensation topology for low-power three-stage OTAs.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2010
Analytical comparison of reversed nested Miller frequency compensation techniques.
Int. J. Circuit Theory Appl., 2010

2009
Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.
IEEE J. Solid State Circuits, 2008

Analytical comparison of frequency compensation techniques in three-stage amplifiers.
Int. J. Circuit Theory Appl., 2008

CMOS current-steering DAC architectures based on the triple-tail cell.
Int. J. Circuit Theory Appl., 2008

Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers.
Int. J. Circuit Theory Appl., 2008

2007
Advances in Reversed Nested Miller Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

CMOS High-CMRR Current Output Stages.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Two CMOS Current Feedback Operational Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

CMOS Miller OTA with Body-Biased Output Stage.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

CMOS voltage feedback current amplifier.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Active reversed nested Miller compensation for three-stage amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
High-performance CMOS pseudo-differential amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

CMOS class AB single-to-differential transconductor.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Optimized design of ECL gates with a power constraint.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Current-steering D/A converter based on triple tail cell.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005


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