Alexis Farcy

According to our database1, Alexis Farcy authored at least 23 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.
IEEE Des. Test, 2016

Heat spreading packaging solutions for hybrid bonded 3D-ICs.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016


2015
Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence.
Microelectron. Reliab., 2015


Stress management strategy to limit die curvature during silicon interposer integration.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
EUROSERVER: Energy Efficient Node for European Micro-Servers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Using TSVs for thermal mitigation in 3D circuits: Wish and truth.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Thermal correlation between measurements and FEM simulations in 3D ICs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
3D integration demonstration of a wireless product with design partitioning.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009
Influence of 3D integration on 2D interconnections and 2D self inductors HF properties.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

First integration of Cu TSV using die-to-wafer direct bonding and planarization.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008


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