Alexey Lopich

According to our database, Alexey Lopich authored at least 14 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision.

Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array.

Alexey Lopich, Piotr Dudek

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps.

Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities.

Alexey Lopich, Piotr Dudek

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.

Alexey Lopich, Piotr Dudek

Int. J. Circuit Theory Appl., 2011

Architecture and design of a programmable 3D-integrated cellular processor array for image processing.

Alexey Lopich, Piotr Dudek

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Live demonstration: Real-time image processing on ASPA2 vision system.

Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A processor element for a mixed signal cellular processor array vision chip.

Stephen J. Carey, Alexey Lopich, Piotr Dudek

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology.

Alexey Lopich, Piotr Dudek

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing.

Alexey Lopich, Piotr Dudek

J. Signal Process. Syst., 2009

A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology.

Piotr Dudek, Alexey Lopich, Viktor Gruev

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

ASPA: Focal Plane digital processor array with asynchronous processing capabilities.

Alexey Lopich, Piotr Dudek

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.

Alexey Lopich, Piotr Dudek

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing.

Alexey Lopich, Piotr Dudek

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006