Alexandro Baldassin

Orcid: 0000-0001-8824-3055

According to our database1, Alexandro Baldassin authored at least 46 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
On the impact of mode transition on phased transactional memory performance.
J. Parallel Distributed Comput., March, 2023

Adaptação automática de conteúdo aplicada em ambiente interativo de aprendizagem individualizada.
Revista Brasileira de Informática na Educ., 2023

Evaluating the Performance of Speculative DOACROSS Loop Parallelization with taskloop.
CoRR, 2023

How to Efficiently Parallelize Irregular DOACROSS Loops Using Fine Granularity and OpenMP Tasks: The SPEC mcf Case.
Proceedings of the OpenMP: Advanced Task-Based, Device and Compiler Programming, 2023

2022
Using Barrier Elision to Improve Transactional Code Generation.
ACM Trans. Archit. Code Optim., 2022

Persistent Memory: A Survey of Programming Support and Implementations.
ACM Comput. Surv., 2022

Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP.
Proceedings of the OpenMP in a Modern World: From Multi-device Support to Meta Programming, 2022

2021
Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

Improving Speculative taskloop in Hardware Transactional Memory.
Proceedings of the OpenMP: Enabling Massive Node-Level Parallelism, 2021

SPHT: Scalable Persistent Hardware Transactions.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

Accelerating Graph Applications Using Phased Transactional Memory.
Proceedings of the Euro-Par 2021: Parallel Processing, 2021

2020
An efficient parallel implementation for training supervised optimum-path forest classifiers.
Neurocomputing, 2020

Using Hardware Transactional Memory to Implement Speculative Privatization in OpenMP.
Proceedings of the Languages and Compilers for Parallel Computing, 2020

Improving Transactional Code Generation via Variable Annotation and Barrier Elision.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory.
Proceedings of the Euro-Par 2020: Parallel Processing, 2020

2019
The Case for Phase-Based Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2019

An optimized unsupervised manifold learning algorithm for manycore architectures.
Inf. Sci., 2019

Semi-supervised and active learning through Manifold Reciprocal kNN Graph for image retrieval.
Neurocomputing, 2019

A Proposal for Supporting Speculation in the OpenMP taskloop Construct.
Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

2018
Data Summarization in the Node by Parameters (DSNP): Local Data Fusion in an IoT Environment.
Sensors, 2018

On the Efficiency of Transactional Code Generation: A GCC Case Study.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Pattern Analysis in Drilling Reports using Optimum-Path Forest.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
FGSCM: A Fine-Grained Approach to Transactional Lock Elision.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Revisiting phased transactional memory.
Proceedings of the International Conference on Supercomputing, 2017

Quaternionic Flower Pollination Algorithm.
Proceedings of the Computer Analysis of Images and Patterns, 2017

2016
Energy-aware scheduling in transactional memory systems.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

On the Harmony Search Using Quaternions.
Proceedings of the Artificial Neural Networks in Pattern Recognition, 2016

2015
Performance implications of dynamic memory allocators on transactional memory systems.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015

2014
Training Optimum-Path Forest on Graphics Processing Units.
Proceedings of the VISAPP 2014, 2014

2013
Transaction Scheduling Using Dynamic Conflict Avoidance.
Int. J. Parallel Program., 2013

Transaction scheduling using conflict avoidance and Contention Intensity.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

2012
A transactional runtime system for the Cell/BE architecture.
J. Parallel Distributed Comput., 2012

Energy-Performance Tradeoffs in Software Transactional Memory.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Vectorized Algorithms for Quadtree Construction and Descent.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

2011
Using multiple abstraction levels to speedup an MPSoC virtual platform simulator.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

LUTS: A Lightweight User-Level Transaction Scheduler.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010
Concurrent programming with revisions and isolation types.
Proceedings of the 25th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2010

STM versus lock-based systems: an energy consumption perspective.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
Exploiting software transactional memory in the context of asymmetric architectures.
PhD thesis, 2009

Characterizing the Energy Consumption of Software Transactional Memory.
IEEE Comput. Archit. Lett., 2009

On the energy-efficiency of software transactional memory.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
An open-source binary utility generator.
ACM Trans. Design Autom. Electr. Syst., 2008

A Software Transactional Memory System for an Asymmetric Processor Architecture.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Automatic Retargeting of Binary Utilities for Embedded Code Generation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2005
Extending the ArchC Language for Automatic Generation of Assemblers.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005


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