Alexandre Levisse

Orcid: 0000-0002-8984-9793

According to our database1, Alexandre Levisse authored at least 42 papers between 2014 and 2024.

Collaborative distances:

Timeline

2014
2016
2018
2020
2022
2024
0
1
2
3
4
5
6
7
8
9
10
3
6
2
4
1
1
2
4
5
6
2
3
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes.
CoRR, 2024

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023
Overflow-free Compute Memories for Edge AI Acceleration.
ACM Trans. Embed. Comput. Syst., October, 2023

Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023

ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.
IEEE Trans. Computers, July, 2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference.
IEEE Trans. Emerg. Top. Comput., 2023

Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022
A Hardware/Software Co-Design Vision for Deep Learning at the Edge.
IEEE Micro, 2022

A Soft SIMD Based Energy Efficient Computing Microarchitecture.
CoRR, 2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021


2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

BLADE: An in-Cache Computing Architecture for Edge Devices.
IEEE Trans. Computers, 2020

Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.
IEEE Access, 2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Functionality Enhanced Memories for Edge-AI Embedded Systems.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

BLADE: A BitLine Accelerator for Devices on the Edge.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Architecture, design and technology guidelines for crosspoint memories.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

High density emerging resistive memories: What are the limits?
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

2014
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination.
Proceedings of the 15th Latin American Test Workshop, 2014


  Loading...