Alexandre Levisse
Orcid: 0000-0002-8984-9793
According to our database1,
Alexandre Levisse
authored at least 40 papers
between 2014 and 2024.
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Bibliography
2024
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024
CoRR, 2024
2023
ACM Trans. Embed. Comput. Syst., October, 2023
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.
IEEE Trans. Computers, July, 2023
An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021
2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Computers, 2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.
IEEE Access, 2020
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
2015
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
2014
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination.
Proceedings of the 15th Latin American Test Workshop, 2014