Alexandre Joannou

Affiliations:
  • University of Cambridge, UK


According to our database1, Alexandre Joannou authored at least 12 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.
IEEE Des. Test, February, 2024

A Suite of Processors to Explore CHERI-RISC-V Micro Architecture.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Architectural Contracts for Safe Speculation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2020
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020


2019
CHERI Concentrate: Practical Compressed Capabilities.
IEEE Trans. Computers, 2019

CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
High-performance memory safety: optimizing the CHERI capability machine.
PhD thesis, 2018


2017

CHERI JNI: Sinking the Java Security Model into the C.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Fast Protection-Domain Crossing in the CHERI Capability-System Architecture.
IEEE Micro, 2016


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