Alexandre Guerre

According to our database, Alexandre Guerre authored at least 15 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Blockgraph proof-of-concept.

David Cordova Morales, Pedro B. Velloso, Alexandre Guerre, Thi Mai Trang Nguyen, Guy Pujolle, Khaldoun Al Agha, Guillaume Dua

Proceedings of the SIGCOMM '21: ACM SIGCOMM 2021 Conference, 2021

2016

Specific Read-Only Data Management for Memory System Optimization.

Gregory Vaumourin, Alexandre Guerre, Thomas Dombek, Denis Barthou

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015

A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures.

Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Julien Mottin, Pascal Vivet, Hela Boussetta, Nicolas Peltier

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

HARS: A hardware-assisted runtime software for embedded many-core architectures.

Yves Lhuillier, Maroun Ojail, Alexandre Guerre, Jean-Marc Philippe, Karim Ben Chehida, Farhat Thabet, Caaliph Andriamisaina, Chafic Jaber, Raphaël David

ACM Trans. Embed. Comput. Syst., 2014

Specific read only data management for memory hierarchy optimization.

Gregory Vaumourin, Thomas Dombek, Alexandre Guerre, Denis Barthou

SIGBED Rev., 2014

Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective.

Yves Lhuillier, Jean-Marc Philippe, Alexandre Guerre, Michal Kierzynka, Ariel Oleksiak

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Early design stage thermal evaluation and mitigation: The locomotiv architectural case.

Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A unified methodology for a fast benchmarking of parallel architecture.

Alexandre Guerre, Jean-Thomas Acquaviva, Yves Lhuillier

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

PACHA: Low Cost Bare Metal Development for Shared Memory Manycore Accelerators.

Alexandre Aminot, Alexandre Guerre, Julien Peeters, Yves Lhuillier

Proceedings of the International Conference on Computational Science, 2013

ARTM: a lightweight fork-join framework for many-core embedded systems.

Maroun Ojail, Raphaël David, Yves Lhuillier, Alexandre Guerre

Proceedings of the Design, Automation and Test in Europe, 2013

2012

SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation.

Nicolas Ventroux, Tanguy Sassolas, Alexandre Guerre, Béatrice Creusillet, Ronan Keryell

Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

2010

SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications.

Nicolas Ventroux, Tanguy Sassolas, Raphaël David, Guillaume Blanc, Alexandre Guerre, Charly Bechara

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Hierarchical Network-on-Chip for Embedded Many-Core Architectures.

Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot

Proceedings of the NOCS 2010, 2010

SESAM: An MPSoC Simulation Environment for Dynamic Application Processing.

Nicolas Ventroux, Alexandre Guerre, Tanguy Sassolas, L. Moutaoukil, Guillaume Blanc, Charly Bechara, Raphaël David

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009

Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study.

Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009