Alexandre F. Tenca

According to our database1, Alexandre F. Tenca authored at least 20 papers between 1997 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
CRT RSA decryption: Modular exponentiation based solely on Montgomery Multiplication.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
A Parallel and Uniform k -Partition Method for Montgomery Multiplication.
IEEE Trans. Computers, 2014

2011
A parallel k-partition method to perform Montgomery Multiplication.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2009
Multi-operand Floating-Point Addition.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2006
Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution.
IEEE Trans. Computers, 2006

2004
A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Efficient scalable VLSI architecture for Montgomery inversion in GF( <i>p</i>).
Integr., 2004

Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2<sup>n</sup>).
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm.
IEEE Trans. Computers, 2003

2002
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2).
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

2001
High-Radix Design of a Scalable Modular Multiplier.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2001

A Design of Radix-2 On-line Division Using LSA Organization.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
A Scalable and Unified Multiplier Architecture for Finite Fields GF(<i>p</i>) and GF(2<sup>m</sup>).
Proceedings of the Cryptographic Hardware and Embedded Systems, 2000

1999
A Scalable Architecture for Montgomery Multiplication.
Proceedings of the Cryptographic Hardware and Embedded Systems, 1999

On the Design of High-Radix On-Line Division for Long Precision.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Long and Fast Up/Down Counters.
IEEE Trans. Computers, 1998

A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997


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