Alexander V. Rylyakov
According to our database1,
Alexander V. Rylyakov
authored at least 63 papers
between 2002 and 2024.
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Bibliography
2024
802 Gbps Coherent Optical Sub-Assembly (COSA) based on a Coupling Modulated Silicon Ring Resonator.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024
2023
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength.
IEEE J. Solid State Circuits, 2023
2020
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength.
IEEE J. Solid State Circuits, 2020
2019
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers.
IEEE J. Solid State Circuits, 2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Monolithically-Integrated 50 Gbps 2pJ/bit Photoreceiver with Cherry-Hooper TIA in 250nm BiCMOS Technology.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A Silicon Photonic Transceiver and Hybrid Tunable Laser for 64 Gbaud Coherent Communication.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
A 34Gbaud Linear Transimpedance Amplifier with Automatic Gain Control for 200Gb/s DP-16QAM Optical Coherent Receivers.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Micro, 2014
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
Exploring the limits of high-speed receivers for multimode VCSEL-based optical links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".
IEEE J. Solid State Circuits, June, 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
IEEE J. Solid State Circuits, 2012
JOCN, 2012
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link.
IEEE J. Solid State Circuits, 2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI.
IEEE J. Solid State Circuits, 2008
A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
2004
IEEE J. Solid State Circuits, 2004
2003
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.
IEEE J. Solid State Circuits, 2003
IBM J. Res. Dev., 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002