Alexander Nadel

Sharad Malik

Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

A Correct-by-Decision Solution for Simultaneous Place and Route.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 29th International Conference, 2017

2016

Bit-Vector Optimization.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2016

Routing under constraints.

[BibT_eX]

[DOI]

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2015

Efficient generation of small interpolants in CNF.

[BibT_eX]

[DOI]

Yakir Vizel

Formal Methods Syst. Des., 2015

Finding Bounded Path in Graph Using SMT for Automatic Clock Routing.

[BibT_eX]

[DOI]

Amit Erez

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014

Accelerated Deletion-based Extraction of Minimal Unsatisfiable Cores.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2014

Ultimately Incremental SAT.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2014, 2014

Bit-Vector Rewriting with Automatic Rule Generation.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 26th International Conference, 2014

2013

Efficient MUS extraction with resolution.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2013

2012

Preprocessing in Incremental SAT.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Efficient SAT Solving under Assumptions.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

2011

From Total Assignment Enumeration to Modern SAT Solver

[BibT_eX]

[DOI]

CoRR, 2011

Generating Diverse Solutions in SAT.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2011, 2011

Implicative Simultaneous Satisfiability and Applications.

[BibT_eX]

[DOI]

Zurab Khasidashvili

Proceedings of the Hardware and Software: Verification and Testing, 2011

2010

Assignment Stack Shrinking.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Boosting minimal unsatisfiable core extraction.

[BibT_eX]

[DOI]

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Applying SMT in symbolic execution of microcode.

[BibT_eX]

[DOI]

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

SAT-based semiformal verification of hardware.

[BibT_eX]

[DOI]

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009

Understanding and improving a modern SAT solver

[BibT_eX]

[DOI]

PhD thesis, 2009

2007

Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.

[BibT_eX]

[DOI]

Ziyad Hanna

Proceedings of the Theory and Applications of Satisfiability Testing, 2007

A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

2006

A Scalable Algorithm for Minimal Unsatisfiable Core Extraction.

[BibT_eX]

[DOI]

Ziyad Hanna

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

2005

A Clause-Based Heuristic for SAT Solvers.

[BibT_eX]

[DOI]

Ziyad Hanna