Alexander Fish
Orcid: 0000-0002-4994-1536
According to our database1,
Alexander Fish
authored at least 115 papers
between 2001 and 2024.
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Bibliography
2024
DIPER: Detection and Identification of Pathogens Using Edit Distance-Tolerant Resistive CAM.
IEEE Trans. Computers, October, 2024
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023).
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
IEEE Access, 2024
Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
2023
On-chip fully reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography.
CoRR, 2023
Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications.
IEEE Access, 2023
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.
IEEE Access, 2023
Toward a Monolithic Pixel Sensor for Heavy Ion Spectroscopy - Pixel Structure Design and Optimization.
IEEE Access, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Mirror<sup>N</sup> PUF: Harvesting Multiple Independent Bits From Each PUF Cell in 65nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Weight Based Current Assisted Photonic Demodulator (WBCAPD) - Expansion towards Neuromorphic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Silicon Proven 1.8 µm × 9.2 µm 65-nm Digital Bit Generator for Hardware Security Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019
Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019
Proceedings of the 10th IFIP International Conference on New Technologies, 2019
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 800-MHz Mixed- V<sub>T</sub> 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
IEEE J. Solid State Circuits, 2018
Delocalisation of one-dimensional marginals of product measures and the capacity of LTI discrete channels.
CoRR, 2018
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Embedded randomness and data dependencies design paradigm: Advantages and challenges.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Utilization of Process and Supply Voltage Random Variations for Random Bit Generation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Access, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Vulnerability of secured IoT memory against localized back side laser fault injection.
Proceedings of the Seventh International Conference on Emerging Security Technologies, 2017
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE J. Solid State Circuits, 2014
Integr., 2014
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Secured Dual Mode Logic (DML) as a countermeasure against Differential Power Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Inf. Theory, 2013
IEEE Trans. Circuits Syst. Video Technol., 2013
Microelectron. J., 2013
Microelectron. J., 2013
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013
IEEE Access, 2013
Proceedings of the 51st Annual Allerton Conference on Communication, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel.
Sensors, 2012
Delay-Doppler channel estimation with almost linear complexity: To Solomon Golomb for the occasion of his 80 birthday mazel tov.
Proceedings of the 2012 IEEE International Symposium on Information Theory, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Biomed. Circuits Syst., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
An efficient implementation of D-Flip-Flop using the GDI technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
High speed and high resolution current winner-take-all circuit in conjunction with adaptive thresholding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Widening the dynamic range of the readout integration circuit for uncooled microbolometer infrared sensors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Ultra low-power DFF based shift registers design for CMOS image sensors applications.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Low power global shutter CMOS active pixel image sensor with ultra-high dynamic range.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
2003
An adaptive center of mass detection system employing a 2-D dynamic element matching algorithm for object tracking.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001