Alexander D. Lopez

According to our database, Alexander D. Lopez authored at least 2 papers between 1983 and 1989.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1989

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology.

Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, Arnold J. Studwell

IEEE J. Solid State Circuits, August, 1989

1983

Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design.

Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983