Alexander Barkalov

Orcid: 0000-0002-4941-3979

Affiliations:
  • University of Zielona Góra, Poland


According to our database1, Alexander Barkalov authored at least 51 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores.
Comput., July, 2024

Reducing the number of LUTs for Mealy FSMs with state transformation.
Int. J. Appl. Math. Comput. Sci., 2024

Hardware Reduction for FSMs With Extended State Codes.
IEEE Access, 2024

2022
Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs
Lecture Notes in Electrical Engineering 922, Springer, ISBN: 978-3-031-16026-4, 2022

Reducing LUT Count for Mealy FSMs With Transformation of States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections.
Int. J. Appl. Math. Comput. Sci., 2022

Improving Characteristics of FSMs With Mixed Codes of Outputs.
IEEE Access, 2022

2021
IPNES - Interpreted Petri Net for Embedded Systems.
Proceedings of the Knowledge-Based and Intelligent Information & Engineering Systems: Proceedings of the 25th International Conference KES-2021, 2021

2020
Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design
Lecture Notes in Electrical Engineering 636, Springer, ISBN: 978-3-030-38294-0, 2020

Improving characteristics of LUT-based Mealy FSMs.
Int. J. Appl. Math. Comput. Sci., 2020

Improving Characteristics of LUT-Based Moore FSMs.
IEEE Access, 2020

2019
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs.
J. Circuits Syst. Comput., 2019

Encoding of Microoperations in FPGA-Based Moore FSMs.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Designing FPGA-Based Mealy FSMs with Two Levels of Logic.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Decreasing Number of LUTs for Moore FSMs.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2018
Hardware Reduction for Lut-Based Mealy FSMs.
Int. J. Appl. Math. Comput. Sci., 2018

Twofold state assignment for FPGA-based mealy FSMs.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Design of CPLD-based mealy FSMs with counters.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Encoding of Terms in LUT-based Mealy FSMs.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

Design of FPGA-based Mealy FSMs with Counters.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

Twofold State Assignment for LUT-based Mealy FSMs.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2017
Design of EMB-Based Moore FSMs.
J. Circuits Syst. Comput., 2017

Designing Moore FSM with extended class codes.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Code sharing in CPLD-based Moore FSMs.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Designing HFPGA-based Mealy FSMs with transformation of output functions.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

CloudBus protocol hardware multi-converter gateway for distributed embedded systems.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Designing HFPGA-based FSMs with counters.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Designing Moore FSM with Transformation of State Codes.
Proceedings of the Computer Information Systems and Industrial Management, 2017

2014
Hardware Reduction in CPLD-Based Moore FSM.
J. Circuits Syst. Comput., 2014

Design of Moore finite state machine with coding space stretching.
Proceedings of the 7th International Conference on Human System Interactions, 2014

Hardware reduction for RAM-based Moore FSMs.
Proceedings of the 7th International Conference on Human System Interactions, 2014

2013
Hardware Reduction in FPGA-Based Moore FSM.
J. Circuits Syst. Comput., 2013

Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes.
Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

EMB - Based Design of Mealy FSM.
Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

Design of FPGA-Based Moore FMSs with Counters.
Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

Synthesis of Moore Finite State Machines Based on Pseudoequivalent States.
Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

Design of moore finite state machine with extended state codes.
Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces, 2013

Hardware reduction for compositional microprogram control unit dedicated for CPLD systems.
Proceedings of the East-West Design & Test Symposium, 2013

Compositional microprogram control unit with operational automaton of transitions.
Proceedings of the East-West Design & Test Symposium, 2013

2011
Control and Adaptation in Telecommunication Systems - Mathematical Foundations
Lecture Notes in Electrical Engineering 94, Springer, ISBN: 978-3-642-20613-9, 2011

Design of microprogrammed controllers to be implemented in FPGAs.
Int. J. Appl. Math. Comput. Sci., 2011

Optimization of microprogram control unit with code sharing.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Hardware reduction for matrix circuit of control Moore automaton.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Synthesis of control unit with refined state encoding for CPLD devices.
Proceedings of the 9th East-West Design & Test Symposium, 2011

2010
Reduction in the number of LUT elements for control units with code sharing.
Int. J. Appl. Math. Comput. Sci., 2010

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Hardware reduction for FSM - Based control units using PAL technology.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Microprogram control unit with code sharing and extended microinstruction format.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
Logic Synthesis for FSM-Based Control Units
Lecture Notes in Electrical Engineering 53, Springer, ISBN: 978-3-642-04308-6, 2009

2008
Logic Synthesis for Compositional Microprogram Control Units
Lecture Notes in Electrical Engineering 22, Springer, ISBN: 978-3-540-69283-6, 2008

2007
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM.
Int. J. Appl. Math. Comput. Sci., 2007


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