Alexander Albicki

According to our database1, Alexander Albicki authored at least 21 papers between 1985 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1996
Extended hyperbolic congruential frequency hop code: generation and bounds for cross- and auto-ambiguity function.
IEEE Trans. Commun., 1996

Reducing power dissipation in CMOS circuits by signal probability based transistor reordering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Low power and high speed multiplication design through mixed number representations.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Efficient testability enhancement for combinational circuit.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
High Throughput Error Control Using Parallel CRC.
VLSI Design, 1994

Low power design using double edge triggered flip-flops.
IEEE Trans. Very Large Scale Integr. Syst., 1994

New advances in path delay fault testing of combinational circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Double Edge Triggered Devices: Speed and Power Considerations.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Bit-Splitting for Testability Enhancement in Scan-Based Design.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Locally clocked microprocessor.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

An asynchronous multiplier.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Self-timed pipeline with adder.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1991
Random Testability of Redundant Circuits.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1989
Comments on "Ternary Scan Design for VLSI Testability".
IEEE Trans. Computers, 1989

An algorithm for voice and data integration on packet-switched local area networks.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
Prioritized access in CSMA networks: a node partitioning approach.
Proceedings of the 13th Conference on Local Computer Networks, 1988

1985
Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control Units.
Proceedings of the Proceedings International Test Conference 1985, 1985

Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules.
Proceedings of the Proceedings International Test Conference 1985, 1985

Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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