Alex R. Bugeja

According to our database, Alex R. Bugeja authored at least 9 papers between 1997 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2006

2005

A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer.

Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja

IEEE J. Solid State Circuits, 2004

2003

A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer.

Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001

Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS.

Alex R. Bugeja, Sung-Ung Kwak

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

High-Speed, High-Precision Digital-Analog Converters Designed for Spectral Performance

Alex R. Bugeja

PhD thesis, 2000

A self-trimming 14-b 100-MS/s CMOS DAC.

Alex R. Bugeja, Bang-Sup Song

IEEE J. Solid State Circuits, 2000

1999

A 14-b, 100-MS/s CMOS DAC designed for spectral performance.

Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig

IEEE J. Solid State Circuits, 1999

1997

A reconfigurable VLSI coprocessing system for the block matching algorithm.

Alex R. Bugeja, W. Yang

IEEE Trans. Very Large Scale Integr. Syst., 1997