Alex Pajuelo

Orcid: 0000-0002-5510-6860

According to our database1, Alex Pajuelo authored at least 26 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Hypervisor Extension for a RISC-V Processor.
CoRR, 2024

2022
Transfer-Learning-Based Intrusion Detection Framework in IoT Networks.
Sensors, 2022

2021
A cost-efficient QoS-aware analytical model of future software content delivery networks.
Int. J. Netw. Manag., 2021

Deep Learning Detection of GPS Spoofing.
Proceedings of the Machine Learning, Optimization, and Data Science, 2021

2018
Platform-Agnostic Steal-Time Measurement in a Guest Operating System.
CoRR, 2018

2016
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.
IEEE Trans. Computers, 2016

Dynamic web worker pool management for highly parallel javascript web applications.
Concurr. Comput. Pract. Exp., 2016

Performance Scalability Analysis of JavaScript Applications with Web Workers.
IEEE Comput. Archit. Lett., 2016

2013
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 2013

2012
The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications.
IEEE Micro, 2012

Optimal task assignment in multithreaded processors: a statistical approach.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2010
On the Problem of Evaluating the Performance of Multiprogrammed Workloads.
IEEE Trans. Computers, 2010

Thread to strand binding of parallel network applications in massive multi-threaded systems.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

Efficient runahead threads.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Code Semantic-Aware Runahead Threads.
Proceedings of the ICPP 2009, 2009

2008
Measuring Operating System Overhead on CMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Runahead Threads to improve SMT performance.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Energy saving through a simple load control mechanism.
SIGARCH Comput. Archit. News, 2007

FAME: FAirly MEasuring Multithreaded Architectures.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Runahead Threads: Reducing Resource Contention in SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
A simple speculative load control mechanism for energy saving.
Proceedings of the 2006 workshop on MEmory performance, 2006

Kilo-instruction processors, runahead and prefetching.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Speculative execution for hiding memory latency.
SIGARCH Comput. Archit. News, 2005

Control-Flow Independence Reuse via Dynamic Vectorization.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2002
Speculative Dynamic Vectorization.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002


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