Alessio Spessot

According to our database, Alessio Spessot authored at least 23 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM.

J. Ganguly, Hiroaki Arimura, Romain Ritzenthaler, H. Bana, J. W. Maes, J. G. Lai, S. Brus, W. Maqsood, R. Sarkar, B. Kannan, Elena Capogreco, V. Machkaoutsan, S. Yoon, Alessio Spessot, M. Givens, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics.

J. P. Bastos, Barry J. O'Sullivan, Yusuke Higashi, Adrian Vaisman Chasin, Jacopo Franco, Hiroaki Arimura, J. Ganguly, Elena Capogreco, Alessio Spessot, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022

Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems.

Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor

IEEE Trans. Very Large Scale Integr. Syst., 2022

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.

Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.

J. P. Bastos, Barry J. O'Sullivan, Jacopo Franco, Stanislav Tyaginov, Brecht Truijen, Adrian Vaisman Chasin, Robin Degraeve, Ben Kaczer, Romain Ritzenthaler, Elena Capogreco, E. Dentoni Litta, Alessio Spessot, Yusuke Higashi, Y. Yoon, V. Machkaoutsan, Pierre Fazan, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.

Alessio Spessot, Shairfe Muhammad Salahuddin, Ricardo Escobar, Romain Ritzenthaler, Yang Xiang, Rahul Budhwani, Eugenio Dentoni Litta, Elena Capogreco, Joao Bastos, Yangyin Chen, Naoto Horiguchi

Proceedings of the IEEE International Memory Workshop, 2022

Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology.

Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm.

Subrat Mishra, Pieter Weckx, Odysseas Zografos, Ji-Yung Lin, Alessio Spessot, Francky Catthoor

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).

Subrat Mishra, Pieter Weckx, Ji-Yung Lin, Ben Kaczer, Dimitri Linten, Alessio Spessot, Francky Catthoor

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation.

Adrian Vaisman Chasin, Jacopo Franco, Erik Bury, Romain Ritzenthaler, Eugenio Dentoni Litta, Alessio Spessot, Naoto Horiguchi, Dimitri Linten, Ben Kaczer

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Device Scaling roadmap and its implications for Logic and Analog platform.

Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert

Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2019

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.

Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.

Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017

SRAM designs for 5nm node and beyond: Opportunities and challenges.

Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs.

Alessio Spessot, Romain Ritzenthaler, Tom Schram, Marc Aoulaiche, Moonju Cho, Maria Toledano-Luque, Naoto Horiguchi, Pierre Fazan

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Assessment of SiGe quantum well transistors for DRAM peripheral applications.

Romain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.

Romain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Christian Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Off-state stress degradation mechanism on advanced p-MOSFETs.

Moonju Cho, Alessio Spessot, Ben Kaczer, Marc Aoulaiche, Romain Ritzenthaler, Tom Schram, Pierre Fazan, Naoto Horiguchi, Dimitri Linten

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Impact of Off State Stress on advanced high-K metal gate NMOSFETs.

Alessio Spessot, Marc Aoulaiche, Moonju Cho, Jacopo Franco, Tom Schram, Romain Ritzenthaler, Ben Kaczer

Proceedings of the 44th European Solid State Device Research Conference, 2014

2013

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.

Marc Aoulaiche, Eddy Simoen, Romain Ritzenthaler, Tom Schram, Hiroaki Arimura, Moonju Cho, Thomas Kauerauf, Guido Groeseneken, Naoto Horiguchi, Aaron Thean, Antonio Federico, Felice Crupi, Alessio Spessot, Christian Caillat, Pierre Fazan, Hyuokju Na, Y. Son, K. B. Noh

Proceedings of the European Solid-State Device Research Conference, 2013

2012

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.

Romain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken, N. Horiguchi, Aaron Thean, Alessio Spessot, Christian Caillat, V. Srividya, Pierre Fazan

Proceedings of the 2012 European Solid-State Device Research Conference, 2012