Alessandro Veronesi
Orcid: 0009-0000-1159-4463
According to our database1,
Alessandro Veronesi
authored at least 7 papers
between 2020 and 2024.
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Bibliography
2024
An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space.
Proceedings of the IEEE European Test Symposium, 2024
2023
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023
2022
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2020
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.
Proceedings of the VLSI-SoC: Design Trends, 2020