Alessandro Strano
According to our database1,
Alessandro Strano
authored at least 24 papers
between 2009 and 2014.
Collaborative distances:
Collaborative distances:
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Bibliography
2014
A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems.
Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014
2013
Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems.
PhD thesis, 2013
ACM Trans. Embed. Comput. Syst., 2013
An efficient, low-cost routing framework for convex mesh partitions to support virtualization.
ACM Trans. Embed. Comput. Syst., 2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip.
IET Comput. Digit. Tech., 2013
2012
Int. J. Embed. Real Time Commun. Syst., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 2012 International Green Computing Conference, 2012
2011
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.
Int. J. Embed. Real Time Commun. Syst., 2011
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Proceedings of the Design, Automation and Test in Europe, 2011
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009