Alessandro Fin

According to our database1, Alessandro Fin authored at least 21 papers between 2000 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2003
A Remote Methodology for Embedded Systems Design and Validation.
Des. Autom. Embed. Syst., 2003

A SystemC-based Framework for Properties Incompleteness Evaluation.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Mixing ATPG and property checking for testing HW/SW interfaces.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

LAERTE++: an Object Oriented High-level TPG for SystemC Designs.
Proceedings of the Forum on specification and Design Languages, 2003

2002
A functional testing framework for embedded systems.
PhD thesis, 2002

Behavioral test generation for the selection of BIST logic.
J. Syst. Archit., 2002

A fault tolerant incremental design methodology.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Genetic Testing Framework for Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2002), 2002

A 1000X speed up for properties completeness evaluation.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Protected IP-core test generation.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002

Emulation-Based Design Errors Identification.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
AMLETO: a multi-language environment for functional test generation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Soft-cores generation by instruction set analysis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Functional test generation for behaviorally sequential models.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

SystemC: a homogenous environment to test embedded systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
An Application of Genetic Algorithms and BDDs to Functional Testing.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

BIST Architectures Selection Based on Behavioral Testing.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

A VHDL Error Simulator for Functional Test Generation.
Proceedings of the 2000 Design, 2000

A Web-CAD methodology for IP-core analysis and simulation.
Proceedings of the 37th Conference on Design Automation, 2000


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