Alessandro Capotondi
Orcid: 0000-0001-8705-0761
According to our database1,
Alessandro Capotondi
authored at least 43 papers
between 2013 and 2024.
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Bibliography
2024
Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip.
Proceedings of the 22nd International Workshop on Worst-Case Execution Time Analysis, 2024
Proceedings of the 2024 Joint International Conference on Computational Linguistics, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
CoRR, 2023
Proceedings of the Seventh Workshop on Natural Language for Artificial Intelligence (NL4AI 2023) co-located with 22th International Conference of the Italian Association for Artificial Intelligence (AIxIA 2023), 2023
A Request for Clarity over the End of Sequence Token in the Self-Critical Sequence Training.
Proceedings of the Image Analysis and Processing - ICIAP 2023, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Exploiting Multiple Sequence Lengths in Fast End to End Training for Image Captioning.
Proceedings of the IEEE International Conference on Big Data, 2023
2022
ExpansionNet v2: Block Static Expansion in fast end to end training for Image Captioning.
CoRR, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An FPGA Overlay for Efficient Real-Time Localization in 1/10th Scale Autonomous Vehicles.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Sensors, 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Leveraging Automated Mixed-Low-Precision Quantization for Tiny Edge Microcontrollers.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Memory-Driven Mixed Low Precision Quantization for Enabling Deep Network Inference on Microcontrollers.
Proceedings of the Third Conference on Machine Learning and Systems, 2020
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020
2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators.
IEEE Trans. Emerg. Top. Comput., 2018
Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
HERO: an open-source research platform for HW/SW exploration of heterogeneous manycore systems.
Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2018
2017
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA.
CoRR, 2017
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017
2016
Programming models and tools for many-core platforms ; Modelli e strumenti di programmazione parallela per piattaforme many-core.
PhD thesis, 2016
Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support.
Parallel Comput., 2016
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
2015
IEEE Trans. Ind. Informatics, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Runtime Support for Multiple Offload-Based Programming Models on Embedded Manycore Accelerators.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015
2014
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
2013
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013