Alessandro Bosi

According to our database, Alessandro Bosi authored at least 5 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, D. Albano, C. Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, D. Burgos, Gabriele Minoia, P. Rossi, Marco Sosio, L. Vignoli, Enrico Temporiti, S. Scouten, S. Jantzi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2019

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.

Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS.

Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani

IEEE J. Solid State Circuits, 2016

27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS.

Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2009

A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver.

Giovanni Cesura, Alessandro Bosi, Francesco Rezzi, Rinaldo Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, Ovidiu Carnu, Thomas Cho

Proceedings of the IEEE International Solid-State Circuits Conference, 2009