Alessandra Menicucci

According to our database, Alessandra Menicucci authored at least 15 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Convolutional Neural Network Design and Evaluation for Real-Time Multivariate Time Series Fault Detection in Spacecraft Attitude Sensors.

Riccardo Gallon, Fabian Schiemenz, Alessandra Menicucci, Eberhard K. A. Gill

CoRR, 2024

Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC.

Michael Rogenmoser, Philip Wiese, Bruno E. Forlin, Frank K. Gürkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini

CoRR, 2024

2023

Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications.

Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Claudio Monteleone

J. Aerosp. Inf. Syst., 2023

2022

Improving CubeSat reliability: Subsystem redundancy or improved testing?

Jasper Bouwmeester, Alessandra Menicucci, Eberhard K. A. Gill

Reliab. Eng. Syst. Saf., 2022

Is RISC-V ready for Space? A Security Perspective.

Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Preventing Soft Errors and Hardware Trojans in RISC-V Cores.

Edian B. Annink, Gerard K. Rauwerda, Edwin A. Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors.

Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone

J. Aerosp. Inf. Syst., August, 2021

Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era.

Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone

Comput. Sci. Rev., 2021

2020

On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor.

Danilo Cappellone, Stefano Di Mascio, Gianluca Furano, Alessandra Menicucci, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Leveraging the Openness and Modularity of RISC-V in Space.

Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone

J. Aerosp. Inf. Syst., November, 2019

On the Criticality of Caches in Fault-Tolerant Processors for Space.

Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Characterization of a RISC-V Microcontroller Through Fault Injection.

Dario Asciolla, Luigi Dilillo, Douglas A. dos Santos, Douglas R. Melo, Alessandra Menicucci, Marco Ottavi

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

The Case for RISC-V in Space.

Stefano Di Mascio, Alessandra Menicucci, Gianluca Furano, Claudio Monteleone, Marco Ottavi

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2016

Qualitative techniques for System-on-Chip test with low-energy protons.

Stefano Di Mascio, Marco Ottavi, Gianluca Furano, Tomasz Szewczyk, Alessandra Menicucci, Luigi Campajola, Francesco Di Capua

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

A novel method for SEE validation of complex SoCs using Low-Energy Proton beams.

Gianluca Furano, Stefano Di Mascio, Tomasz Szewczyk, Alessandra Menicucci, Luigi Campajola, Francesco Di Capua, Andrea Fabbri, Marco Ottavi

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016