Alen Bardizbanyan

According to our database1, Alen Bardizbanyan authored at least 15 papers between 2010 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Probabilistic timing analysis on time-randomized platforms for the space domain.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Logic filter cache for wide-VDD-range processors.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Practical way halting by speculatively accessing halt tags.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Data Access Techniques for Enhanced Energy Efficiency and Performance in In-order Pipelines.
PhD thesis, 2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores.
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Exploring early and late ALUs for single-issue in-order pipelines.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD<sup>3</sup>).
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Designing a practical data filter cache to improve both energy efficiency and performance.
ACM Trans. Archit. Code Optim., 2013

Speculative tag access for reduced energy dissipation in set-associative L1 data caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Improving data access efficiency by using a tagless access buffer (TAB).
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
Configurable RTL model for level-1 caches.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Generation and Exploration of Layouts for Area-Efficient Barrel Shifters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010


  Loading...