Aleksandar Simevski

Orcid: 0000-0002-6247-4346

According to our database1, Aleksandar Simevski authored at least 22 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A design concept for radiation hardened RADFET readout system for space applications.
Microprocess. Microsystems, April, 2022

Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022

2021
Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters.
CoRR, 2021

2020
PISA: Power-robust Multiprocessor Design for Space Applications.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Review of Particle Detectors for Space-Borne Self-Adaptive Fault-Tolerant Systems.
Proceedings of the IEEE East-West Design & Test Symposium, 2020

Design of Radiation Hardened RADFET Readout System for Space Applications.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Simulation-based Verification of the Youngest-First Round-Robin Core Gating Pattern.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

A Particle Detector Based on Pulse Stretching Inverter Chain.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Power/Area-Optimized Fault Tolerance for Safety Critical Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
Theoretical aspects of a design method for programmable NMR voters.
Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

2016
Implementation of a real time unit for satellite applications.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Architectural framework for dynamically adaptable multiprocessors regarding aging, fault tolerance, performance and power consumption.
PhD thesis, 2015

2014
Investigating Core-Level N-Modular Redundancy in Multiprocessors.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Increasing multiprocessor lifetime by Youngest-First Round-Robin core gating patterns.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Automated integration of fault injection into the ASIC design flow.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Platform for automated HW/SW co-verification, testing and simulation of microprocessors.
Proceedings of the 13th Latin American Test Workshop, 2012

Scalable design of a programmable NMR voter with inputs' state descriptor and self-checking capability.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Low-complexity integrated circuit aging monitor.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011


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