Alejandro Millán

Orcid: 0000-0002-1788-8574

Affiliations:
  • University of Seville, Spain


According to our database1, Alejandro Millán authored at least 21 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2020
Address-encoded byte order.
Microprocess. Microsystems, 2020

Using the complement of the cosine to compute trigonometric functions.
EURASIP J. Adv. Signal Process., 2020

2016
Fast Hardware Implementations of Static P Systems.
Comput. Informatics, 2016

2012
Long-term on-chip verification of systems with logical events scattered in time.
Microprocess. Microsystems, 2012

2011
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation.
IEEE Trans. Instrum. Meas., 2011

Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells.
J. Low Power Electron., 2011

2010
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies.
J. Low Power Electron., 2010

Design and implementation of a suitable core for on-chip long-term verification.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

2008
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Improving the Performance of Static CMOS Gates by Using Independent Bodies.
J. Low Power Electron., 2007

Design of a FFT/IFFT module as an IP core suitable for embedded systems.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Static Power Consumption in CMOS Gates Using Independent Bodies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Accurate Logic-Level Current Estimation for Digital CMOS Circuits.
J. Low Power Electron., 2006

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

2005
Logic-Level Fast Current Simulation for Digital CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Signal Sampling Based Transition Modeling for Digital Gates Characterization.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2003

Internode: Internal Node Logic Computational Model.
Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002


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