Alejandro Cabrera Aldaya

Orcid: 0000-0002-1544-6772

Affiliations:
  • Tampere University, Finland
  • Universidad Tecnológica de la Habana José Antonio Echeverría (CUJAE), La Habana, Cuba (former)


According to our database1, Alejandro Cabrera Aldaya authored at least 13 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
HyperDegrade: From GHz to MHz Effective CPU Frequencies.
Proceedings of the 31st USENIX Security Symposium, 2022

2021
Online Template Attacks: Revisited.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

2020
From A to Z: Projective coordinates leakage in the wild.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

When one vulnerable primitive turns viral: Novel single-trace attacks on ECDSA and RSA.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Certified Side Channels.
Proceedings of the 29th USENIX Security Symposium, 2020

Déjà Vu: Side-Channel Analysis of Mozilla's NSS.
Proceedings of the CCS '20: 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020

2019
Cache-Timing Attacks on RSA Key Generation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Memory Tampering Attack on Binary GCD Based Inversion Algorithms.
Int. J. Parallel Program., 2019

2018
Port Contention for Fun and Profit.
IACR Cryptol. ePrint Arch., 2018

2017
SPA vulnerabilities of the binary extended Euclidean algorithm.
J. Cryptogr. Eng., 2017

Side-channel analysis of the modular inversion step in the RSA key generation algorithm.
Int. J. Circuit Theory Appl., 2017

2016
AES T-Box tampering attack.
J. Cryptogr. Eng., 2016

2012
Real-time FPGA connected component labeling system.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


  Loading...