Alec Lu

Orcid: 0000-0002-3315-7368

According to our database1, Alec Lu authored at least 19 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms.
ACM Trans. Reconfigurable Technol. Syst., September, 2024

Quasar-ViT: Hardware-Oriented Quantization-Aware Architecture Search for Vision Transformers.
Proceedings of the 38th ACM International Conference on Supercomputing, 2024

FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

2023
CHIP-KNNv2: A Configurable and High-Performance K-Nearest Neighbors Accelerator on HBM-based FPGAs.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors.
ACM Trans. Reconfigurable Technol. Syst., 2022

Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking.
ACM Trans. Reconfigurable Technol. Syst., 2022

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding.
Proceedings of the Computer Vision - ECCV 2022, 2022

FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Hardware-efficient stochastic rounding unit design for DNN training: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
Rethinking Integer Divider Design for FPGA-Based Soft-Processors.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019


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